A monolithic pixelated silicon detector designed for high time resolution has been produced in the SG13G2 130 nm SiGe BiCMOS technology of IHP Mikroelektronik. This proof-of-concept chip contains hexagonal pixels of 65 μm and 130 μm side. The SiGe front-end electronics implemented provides an equivalent noise charge of 90 and 160 electrons for a pixel capacitance of 70 and 220 fF, respectively, and a total time walk of less than 1 ns. Lab measurements with a 90Sr source show a time resolution of the order of 50 ps. This result is competitive with silicon technologies that integrate an avalanche gain mechanism.
A monolithic silicon pixel detector prototype has been produced in the SiGe BiCMOS SG13G2 130 nm node technology by IHP. The ASIC contains a matrix of hexagonal pixels with pitch of approximately 100 $μ$m. Three analog pixels were calibrated in laboratory with radioactive sources and tested in a 180 GeV/c pion beamline at the CERN SPS. A detection efficiency of $\left(99.9^{+0.1}_{-0.2}\right)$% was measured together with a time resolution of $(36.4 \pm 0.8)$ps at the highest preamplifier bias current working point of 150 $μ$A and at a sensor bias voltage of 160 V. The ASIC was also characteri…
SiGe BiCMOS technology can be used to produce ultra-fast, low-power silicon pixel sensors that provide state-of-the-art time resolution even without an internal gain mechanism. The development of such sensors requires the identification of the main factors that may degrade the timing performance and the characterisation of the dependance of the sensor time resolution on the amplifier power consumption. Measurements with a $ \mathrm{^{90}Sr} $ source of a prototype sensor produced in SG13G2 technology from IHP Microelectronics, shows a time resolution of 140 ps at an amplifier current of 7 $ \m…
A linear redriver circuit implements multi-band equalization techniques to efficiently compensate for high-frequency channel loss and extend high-speed wireline link reach. Input and output stage emitter-follower buffers with dual AC and DC paths provide programmable low-frequency peaking for channel skin effect, while a continuous-time linear equalizer (CTLE) utilizes RC degeneration in the input stage for mid-band peaking and a subsequent feedback structure contributes to additional high-frequency peaking to compensate for the additional dielectric loss effects. A variable-gain amplifier (VG…
This paper presents a small-area monolithic pixel detector ASIC designed in 130 nm SiGe BiCMOS technology for the upgrade of the pre-shower detector of the FASER experiment at CERN. The purpose of this prototype is to study the integration of fast front-end electronics inside the sensitive area of the pixels and to identify the configuration that could satisfy at best the specifications of the experiment. Self-induced noise, instabilities and cross-talk were minimised to cope with the several challenges associated to the integration of pre-amplifiers and discriminators inside the pixels. The m…
A low power cascode SiGe BiCMOS low noise amplifier (LNA) with current reuse and zero-pole cancellation is presented for ultra-wideband (UWB) application. The LNA is composed of cascode input stage and common emitter (CE) output stage with dual loop feedbacks. The novel cascode-CE current reuse topology replaces the traditional two stages topology so as to obtain low power consumption. The emitter degenerative inductor in input stage is adopted to achieve good input impedance matching and noise performance. The two poles are introduced by the emitter inductor, which will degrade the gain perfo…
The TT-PET collaboration is developing a PET scanner for small animals with 30 ps time-of-flight resolution and sub-millimetre 3D detection granularity. The sensitive element of the scanner is a monolithic silicon pixel detector based on state-of-the-art SiGe BiCMOS technology. The first ASIC prototype for the TT-PET was produced and tested in the laboratory and with minimum ionizing particles. The electronics exhibit an equivalent noise charge below 600 e- RMS and a pulse rise time of less than 2 ns, in accordance with the simulations. The pixels with a capacitance of 0.8 pF were measured to …
The ForwArd Search ExpeRiment (FASER) is an experiment searching for new light and weakly-interacting particles at CERN's Large Hadron Collider. FASER is composed of different sub-detectors, including silicon microstrip detectors, scintillator counters and an electromagnetic calorimeter. In this paper, a new preshower detector for the FASER experiment is presented. The new detector, based on monolithic pixel ASICs, will provide excellent spatial and time resolutions and a large charge dynamic range. First results from a prototype chip produced by IHP in 130 nm SiGe BiCMOS technology are shown.
The TT-PET collaboration is developing a small animal TOF-PET scanner based on monolithic silicon pixel sensors in SiGe BiCMOS technology. The demonstrator chip, a small-scale version of the final detector ASIC, consists of a 3 x 10 pixel matrix integrated with the front-end, a 50 ps binning TDC and read out logic. The chip, thinned down to 100 μm and backside metallized, was operated at a voltage of 180 V. The tests on a beam line of minimum ionizing particles show a detection efficiency greater than 99.9 % and a time resolution down to 110 ps.
Time-of-flight measurement is an important advancement in PET scanners to improve image reconstruction with a lower delivered radiation dose. This article describes the monolithic ASIC for the TT-PET project, a novel idea for a high-precision PET scanner for small animals. The chip uses a SiGe Bi-CMOS process for timing measurements, integrating a fully-depleted pixel matrix with a low-power BJT-based front-end per channel, integrated on the same 100 $μ m$ thick die. The target timing resolution is 30 ps RMS for electrons from the conversion of 511 keV photons. A novel synchronization scheme u…
Initial performance assessment and calibration techniques of the production monolithic silicon pixel detector ASIC for the detection of electromagnetic showers of TeV energy in the FASER experiment at the LHC
The proof-of-concept prototype of the Picosecond Avalanche Detector, a multi-PN junction monolithic silicon detector with continuous gain layer deep in the sensor depleted region, was tested with a beam of 180 GeV pions at the CERN SPS. The prototype features low noise and fast SiGe BiCMOS frontend electronics and hexagonal pixels with 100 μm pitch. At a sensor bias voltage of 125 V, the detector provides full efficiency and average time resolution of 30, 25 and 17 ps in the overall pixel area for a power consumption of 0.4, 0.9 and 2.7 W/cm^2, respectively. In this first prototype the time re…
The Picosecond Avalanche Detector is a multi-junction silicon pixel detector based on a $\mathrm{(NP)_{drift}(NP)_{gain}}$ structure, devised to enable charged-particle tracking with high spatial resolution and picosecond time-stamp capability. It uses a continuous junction deep inside the sensor volume to amplify the primary charge produced by ionizing radiation in a thin absorption layer. The signal is then induced by the secondary charges moving inside a thicker drift region. A proof-of-concept monolithic prototype, consisting of a matrix of hexagonal pixels with 100 $μ$m pitch, has been pr…
