一种面向模拟存内计算的精度优化型定点近存数字处理单元
A Precision-Optimized Fixed-Point Near-Memory Digital Processing Unit for Analog In-Memory Computing
AI总结：
针对现有模拟存内计算系统采用FP16运算存在的并行性不足、延迟高问题，提出基于定点运算的近存数字处理单元NMPU，在14nm工艺下实现，相较FP16方案大幅提升速度、缩减面积，精度损失极小。
摘要：
模拟存内计算（Analog In-Memory Computing, AIMC）是一种用于实现快速、高能效深度学习（Deep Learning, DL）推理的新兴技术。然而，需要一定量的数字后处理来应对电路失配以及存储器件相关的非理想特性。高效的近存数字逻辑对于维持AIMC的高面积/能效和低延迟至关重要。现有系统采用16位浮点数（Floating Point 16, FP16）运算，并行化能力有限且延迟较高。为克服这些局限，我们提出了一种基于定点运算的近存数字处理单元（Near-Memory digital Processing Unit, NMPU）。它在最小化面积开销的同时，实现了与现有方法相当的精度以及更高的计算吞吐量。此外，NMPU支持标准的深度学习激活步骤，例如ReLU和批归一化（Batch Normalization）。我们采用14纳米CMOS工艺完成了NMPU设计的物理实现，并提供了详细的性能、功耗和面积评估。我们通过使用一款AIMC芯片的数据验证了NMPU的有效性，结果表明，搭载所提出NMPU的仿真AIMC系统性能优于现有基于FP16的实现方案，可实现139×的速度提升、7.8×的面积缩减，且功耗水平具有竞争力。此外，在分别用CIFAR10/CIFAR100数据集训练的ResNet9/ResNet32网络上进行基准测试时，我们的方法实现了86.65%/65.06%的推理精度，与FP16基线相比，精度下降仅为0.12%/0.4%。
英文摘要：
Analog In-Memory Computing (AIMC) is an emerging technology for fast and energy-efficient Deep Learning (DL) inference. However, a certain amount of digital post-processing is required to deal with circuit mismatches and non-idealities associated with the memory devices. Efficient near-memory digital logic is critical to retain the high area/energy efficiency and low latency of AIMC. Existing systems adopt Floating Point 16 (FP16) arithmetic with limited parallelization capability and high latency. To overcome these limitations, we propose a Near-Memory digital Processing Unit (NMPU) based on fixed-point arithmetic. It achieves competitive accuracy and higher computing throughput than previous approaches while minimizing the area overhead. Moreover, the NMPU supports standard DL activation steps, such as ReLU and Batch Normalization. We perform a physical implementation of the NMPU design in a 14 nm CMOS technology and provide detailed performance, power, and area assessments. We validate the efficacy of the NMPU by using data from an AIMC chip and demonstrate that a simulated AIMC system with the proposed NMPU outperforms existing FP16-based implementations, providing 139$\times$ speed-up, 7.8$\times$ smaller area, and a competitive power consumption. Additionally, our approach achieves an inference accuracy of 86.65 %/65.06 %, with an accuracy drop of just 0.12 %/0.4 % compared to the FP16 baseline when benchmarked with ResNet9/ResNet32 networks trained on the CIFAR10/CIFAR100 datasets, respectively.
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