封装模拟核的混合信号SOC测试规划
Test Planning for Mixed-Signal SOCs with Wrapped Analog Cores
摘要：
如今，许多SOC都包含数字和模拟嵌入式内核。尽管这种混合信号SOC的测试成本明显高于数字SOC，但该领域的大多数先前研究都只集中在数字内核上。我们提出了一种低成本的测试开发方法，混合信号SOC，允许模拟和数字内核进行测试，以统一的方式，从而最大限度地降低整体测试成本。SOC中的模拟核被封装，使得它们可以使用数字测试访问机制（TAM）来访问。我们评估使用模拟测试包装器的面积开销和测试时间的影响。为了减少面积开销，我们提出了一个模拟测试包装优化技术，然后结合TAM优化的成本导向的启发式方法进行测试调度。我们还证明了使用模拟包装的可行性，提出了晶体管级模拟包装和一个代表性的核心。我们提出了测试调度的ITC'02基准SOC，已增加了五个模拟核心的实验结果。
英文摘要：
Many SOCs today contain both digital and analog embedded cores. Even though the test cost for such mixed-signal SOCs is significantly higher than that for digital SOCs, most prior research in this area has focused exclusively on digital cores. We propose a low-cost test development methodology for mixed-signal SOCs that allows the analog and digital cores to be tested in a unified manner, thereby minimizing the overall test cost. The analog cores in the SOC are wrapped such that they can be accessed using a digital test access mechanism (TAM). We evaluate the impact of the use of analog test wrappers on area overhead and test time. To reduce area overhead, we present an analog test wrapper optimization technique, which is then combined with TAM optimization in a cost-oriented heuristic approach for test scheduling. We also demonstrate the feasibility of using analog wrappers by presenting transistor-level simulations for an analog wrapper and a representative core. We present experimental results on test scheduling for an ITC'02 benchmark SOC that has been augmented with five analog cores.
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