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arXiv 2306.03487quant-phcs.ET

面向动态现场可编程中性原子阵列处理器的量子电路编译

Compiling Quantum Circuits for Dynamically Field-Programmable Neutral Atoms Array Processors

Daniel Bochen Tan, Dolev Bluvstein, Mikhail D. Lukin, Jason Cong

AI总结:

本文针对动态现场可编程中性原子阵列处理器提出布局综合方法,将问题形式化为SMT并引入贪心启发式,使编译电路的双量子比特门数量相比固定架构最多减少5.1倍。

摘要:

动态现场可编程量子比特阵列(DPQA)近年来已成为量子信息处理的一个有前景的平台。在DPQA中,原子量子比特被选择性地加载到可在计算过程中重新配置的光学陷阱阵列中。利用量子比特传输和并行的纠缠量子操作,不同的量子比特对,即使是初始相距很远的量子比特,也可以在量子程序执行的不同阶段实现纠缠。这种可重构性和非局域连接性给编译带来了新的挑战,尤其是在布局综合步骤中,该步骤负责放置和布线量子比特并调度量子门。在本文中,我们考虑一种包含多个阵列并支持二维阵列移动的DPQA架构,该架构代表了前沿的实验平台。在该架构内,我们对状态空间进行离散化,并将布局综合形式化为一个可满足性模理论问题,该问题可以由现有求解器在电路深度方面最优地求解。对于一组由具有复杂连接性的随机图生成的基准电路,我们的编译器OLSQ-DPQA在小规模问题实例上将双量子比特纠缠门的数量减少了1.7倍,相比之下,固定平面架构上的最优编译结果更差。为了进一步提高该方法的可扩展性和实用性,我们引入了一种受经典集成电路布线中迭代剥离方法启发的贪心启发式算法。通过使用结合了贪心方法和最优方法的混合方法,我们证明了基于DPQA的编译电路与网格固定架构相比具有更低的扩展开销,对于90量子比特的量子电路,双量子比特门减少了5.1倍。这些方法使得中性原子量子计算机能够实现可编程的复杂量子电路,同时也为未来的编译器和未来的硬件选择提供了参考。

英文摘要:

Dynamically field-programmable qubit arrays (DPQA) have recently emerged as a promising platform for quantum information processing. In DPQA, atomic qubits are selectively loaded into arrays of optical traps that can be reconfigured during the computation itself. Leveraging qubit transport and parallel, entangling quantum operations, different pairs of qubits, even those initially far away, can be entangled at different stages of the quantum program execution. Such reconfigurability and non-local connectivity present new challenges for compilation, especially in the layout synthesis step which places and routes the qubits and schedules the gates. In this paper, we consider a DPQA architecture that contains multiple arrays and supports 2D array movements, representing cutting-edge experimental platforms. Within this architecture, we discretize the state space and formulate layout synthesis as a satisfiability modulo theories problem, which can be solved by existing solvers optimally in terms of circuit depth. For a set of benchmark circuits generated by random graphs with complex connectivities, our compiler OLSQ-DPQA reduces the number of two-qubit entangling gates on small problem instances by 1.7x compared to optimal compilation results on a fixed planar architecture. To further improve scalability and practicality of the method, we introduce a greedy heuristic inspired by the iterative peeling approach in classical integrated circuit routing. Using a hybrid approach that combined the greedy and optimal methods, we demonstrate that our DPQA-based compiled circuits feature reduced scaling overhead compared to a grid fixed architecture, resulting in 5.1X less two-qubit gates for 90 qubit quantum circuits. These methods enable programmable, complex quantum circuits with neutral atom quantum computers, as well as informing both future compilers and future hardware choices.

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