To increase density of superconductor digital and neuromorphic circuits by 10x and reach integration scale of $10^8$ Josephson junctions (JJs) per chip, we developed a new fabrication process on 200-mm wafers, using self-shunted Nb/Al-AlOx/Nb JJs and kinetic inductors. The process has a layer of JJs, a layer of resistors, and 10 fully planarized superconducting layers: 8 Nb layers and 2 layers of high kinetic inductance materials, Mo$_2$N and NbN, with sheet inductance of 8 pH/sq and 3 pH/sq, respectively. NbN films were deposited by two methods: with $T_c$=15.5 K by reactive sputtering of a Nb target in Ar+N$_2$ mixture; with $T_c$ in the range from 9 K to 13 K by plasma-enhanced chemical vapor deposition (PECVD) using Tris(diethylamido)(tert-butylimido)niobium(V) metalorganic precursor. PECVD of NbN was investigated to obtain conformal deposition and filling narrow trenches and vias with high depth-to-width ratios, which was not possible to achieve using sputtering and other physical vapor deposition (PVD) methods at temperatures below $200 ^oC$ required to prevent degradation of Nb/Al-AlOx/Nb junctions. Nb layers with 200 nm thickness are used in the process layer stack as ground planes to maintain a high level of interlayer shielding and low intralayer mutual coupling, for passive transmission lines with wave impedances matching impedances of JJs, typically <=50 $Ω$, and for low-value inductors. NbN and NbN/Nb bilayer are used for cell inductors. Using NbN/Nb bilayers and individual pattering of both layers to form inductors allowed us to minimize parasitic kinetic inductance associated with interlayer vias and connections to JJs as well as to increase critical currents of the vias. Fabrication details and results of electrical characterization of NbN films, wires, and vias, and comparison with Nb properties are given.
We are developing a superconductor electronics fabrication process with up to nine planarized superconducting layers, stackable stud vias, self-shunted Nb/AlOx-Al/Nb Josephson junctions, and one layer of MoNx kinetic inductors. The minimum feature size of resistors and inductors in the process is 250 nm. We present data on the mutual inductance of Nb stripline and microstrip inductors with linewidth and spacing from 250 nm to 1 μm made on the same or adjacent Nb layers, as well as the data on the linewidth and resistance uniformity.
We present our new fabrication Process for Superconductor Electronics (PSE2) that integrates two (2) layers of Josephson junctions in a fully planarized multilayer process on 200-mm wafers. The two junction layers can be, e.g., conventional Superconductor-Insulator-Superconductor (SIS) Nb/Al/AlO_x/Nb junctions with the same or different Josephson critical current densities, J_c. The process also allows integration of high-J_c Superconductor-Ferromagnet-Superconductor (SFS) or SFS'S JJs on the first junction layer with Nb/Al/AlO_x/Nb trilayer junctions on the second junction layer, or vice vers…
We present the use of a commercially available fixed-angle multi-wavelength ellipsometer for quickly measuring the thickness of NbN thin films for the fabrication and performance improvement of superconducting nanowire single photon detectors. The process can determine the optical constants of absorbing thin films, removing the need for inaccurate approximations. The tool can be used to observe oxidation growth and allows thickness measurements to be integrated into the characterization of various fabrication processes.
We have developed a novel fabrication process for ultra-small, full-epitaxial NbN Josephson junctions on a silicon (Si) substrate. A full-epitaxial NbN/AlN/NbN tri-layer was grown on a Si (100) wafer with a (200)-oriented TiN buffer layer. It was patterned into Josephson junctions by an electron beam lithography (EBL) for junction definition followed by a reactive ion etch (RIE). A chemical mechanical polishing (CMP) process and an additional RIE by using CHF$_3$ gas formed reliable electrical contacts between the junction counter electrodes and the wiring layer. All fabricated junctions, with…
We present a new process for fabricating vertical NbN-MgO-NbN Josephson junctions using self-aligned silicon nitride spacers. It allows for a wide range of junction areas from 0.02 um^2 to several 100 um^2. At the same time, it is suited for the implementation of complex microwave circuits with transmission line impedances ranging from < 1 Ohm to > 1 kOhm. The constituent thin films and the finished junctions are characterized. The latter are shown to have high gap voltages (> 4 mV) and low sub-gap leakage currents.
A fabrication process for Nb/Al-AlOx/Nb Josephson junctions (JJs) with sizes down to 200 nm has been developed on a 200-mm-wafer tool set typical for CMOS foundry. This process is the core of several nodes of a roadmap for fully-planarized fabrication processes for superconductor integrated circuits with 4, 8, and 10 niobium layers developed at MIT Lincoln Laboratory. The process utilizes 248 nm photolithography, anodization, high-density plasma etching, and chemical mechanical polishing (CMP) for planarization of SiO$_2$ interlayer dielectric. JJ electric properties and statistics such as on-…
The fabrication of high-quality thin superconducting films is essential for single-photon detectors. Their device performance is crucially affected by their material parameters, thus requiring reliable and nondestructive characterization methods after the fabrication and patterning processes. Important material parameters to know are the resistivity, superconducting transition temperature, relaxation time of quasiparticles, and uniformity of patterned wires. In this work, we characterize micro-patterned thin NbN films by using transport measurements in magnetic fields. We show that from the in…
Superconducting nanowires undergoing quantum phase-slips have potential for impact in electronic devices, with a high-accuracy quantum current standard among a possible toolbox of novel components. A key element of developing such technologies is to understand the requirements for, and control the production of, superconducting nanowires that undergo coherent quantum phase-slips. We present three fabrication technologies, based on using electron-beam lithography or neon focussed ion-beam lithography, for defining narrow superconducting nanowires, and have used these to create nanowires in niob…
Data are presented on mutual and self-inductance of various inductors used in multilayered superconductor integrated circuits: microstrips and striplines with widths of signal traces from 250 nm to a few micrometers, located on the same circuit layer at various distances from each other (from 250 nm to a few micrometers) and/or on different layers spaced vertically; effect of long slits in the ground plane(s) along the inductors on their mutual inductance; inductance of right-angled bends; inductance of meanders. Simple analytical expressions for mutual and self-inductance of the basic inducto…
Superconductor digital electronics using Josephson junctions as ultrafast switches and magnetic-flux encoding of information was proposed over 30 years ago as a sub-terahertz clock frequency alternative to semiconductor electronics based on complementary metal-oxide-semiconductor (CMOS) transistors. Recently, interest in developing superconductor electronics has been renewed due to a search for energy saving solutions in applications related to high-performance computing. The current state of superconductor electronics and fabrication processes are reviewed in order to evaluate whether this el…
We review the salient features of two advanced nodes of an 8-Nb-layer fully planarized process developed recently at MIT Lincoln Laboratory for fabricating Single Flux Quantum(SFQ) digital circuits with very large scale integration on 200-mm wafers: the SFQ4ee and SFQ5ee nodes, where 'ee' denotes the process is tuned for energy efficient SFQ circuits. The former has eight superconducting layers with 0.5 μm minimum feature size and a 2 Ω/sq Mo layer for circuit resistors. The latter has nine superconducting layers: eight Nb wiring layers with the minimum feature size of 350 nm and a thin superc…
Using a fully automated cryogenic wafer prober, we measured superconductor fabrication process control monitors and simple integrated circuits on 200 mm wafers at 4.4 K, including SQIF-based magnetic field sensors, SQUID-based circuits for measuring inductors, Nb/Al-AlOx/Nb Josephson junctions, test structures for measuring critical current of superconducting wires and vias, resistors, etc., to demonstrate the feasibility of using the system for characterizing niobium superconducting devices and integrated circuits on a wafer scale. Data on the wafer-scale distributions of the residual magneti…
We have successfully fabricated micron-scale Cu-AlO$_{x} $-Al-NbN normal metal-insulator-superconductor (NIS) tunnel junction devices, using pulsed laser deposition (PLD) for NbN film growth, and electron-beam lithography and shadow evaporation for the final device fabrication. The subgap conductance of these devices exhibit a strong temperature dependence, rendering them suitable for thermometry from $\sim$ 0.1 K all the way up to the superconducting transition temperature of the NbN layer, which was here $\sim 11$ K, but could be extended up to $\sim 16$ K in our PLD chamber. Our data fits w…
We develop an ac-biased shift register introduced in our previous work (V.K. Semenov et al., IEEE Trans. Appl. Supercond., vol. 25, no. 3, 1301507, June 2015) into a benchmark circuit for evaluation of superconductor electronics fabrication technology. The developed testing technique allows for extracting margins of all individual cells in the shift register, which in turn makes it possible to estimate statistical distribution of Josephson junctions in the circuit. We applied this approach to successfully test registers having 8, 16, 36, and 202 thousand cells and, respectively, about 33000, 6…
Inductance of superconducting thin-film inductors and structures with linewidth down to 250 nm has been experimentally evaluated. The inductors include various striplines and microstrips, their 90-degree bends and meanders, interlayer vias, etc., typically used in superconducting digital circuits. The circuits have been fabricated by a fully planarized process with 8 niobium layers, developed at MIT Lincoln Laboratory for very-large-scale superconducting integrated circuits. Excellent run-to-run reproducibility and inductance uniformity of better than 1% across 200-mm wafers have been found. I…
Disentangling superconductor and dielectric microwave losses in sub-micron $\rm Nb$/$\rm TEOS-SiO_2$ interconnects using a multi-mode microstrip resonator
Flux transformers are the necessary component of all superconductor digital integrated circuits utilizing ac power for logic cell excitation and clocking, and flux biasing, e.g., Adiabatic Quantum Flux Parametron (AQFP), Reciprocal Quantum Logic, superconducting sensor arrays, qubits, etc. We consider limitations to the integration scale (device number density) imposed by the critical current of the ac power transmission lines and cross coupling between the adjacent transformers. The former sets the minimum line width and the mutual coupling length in the transformer, whereas the latter sets t…
A fabrication process has been developed for fully planarized Nb-based superconducting inter-layer connections (vias) with minimum size down to 250 nm for superconductor very large scale integrated (VLSI) circuits with 8 and 10 superconducting layers on 200-mm wafers. Instead of single Nb wiring layers, it utilizes Nb/Al/Nb trilayers for each wiring layer to form Nb pillars (studs) providing vertical connections between the wires etched in the bottom layer of the trilayer and the next wiring layer that is also deposited as a Nb/Al/Nb trilayer. This technology makes possible a dramatic increase…
Data are presented on inductance of various features used in superconductor digital integrated circuits such as microstrip and stripline inductors with linewidths down to 120 nm and different combinations of ground plane layers, effect of perforations of various sizes in the ground planes and their distance to the inductors on inductance, inductance of vias of various sizes between adjacent layers and composite vias between distant superconducting layers. Effects of magnetic flux trapping in ground plane moats on coupling to nearby inductors are discussed for circuit cooling in a residual fiel…
We present results of a fabrication-process development for the lithographic pattern transfer into the sub-100nm range by combining electron-beam lithography and reactive dry etching to obtain high quality niobium-based light-sensitive superconducting devices. To achieve this spatial resolution, we systematically investigated the stability of the positive organic etching masks ZEP 520A and PMMA 950k in different properly operated fluoride based plasma discharges. The chemically more robust ZEP 520A was used for defining the nanoscaled superconductors during the dry plasma etching. Our etching …
