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arXiv 1602.03546cond-mat.supr-con
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超导数字电子:可扩展性和能源效率问题

Superconductor Digital Electronics: Scalability and Energy Efficiency Issues

Sergey K. Tolpygo

摘要:

30多年前,提出了使用约瑟夫森结作为超快开关和信息的磁通量编码的超导体数字电子学,作为基于互补金属氧化物半导体(CMOS)晶体管的半导体电子学的亚太赫兹时钟频率替代品。最近,由于在与高性能计算相关的应用中寻找节能解决方案,对开发超导电子学的兴趣已经重新燃起。超导体电子学和制造工艺的当前状态进行审查,以评估这种电子学是否可扩展到一个非常大规模的集成电路(VLSI)所需的实现与CMOS处理器的计算复杂性。麻省理工学院林肯实验室的一个完全平坦化的过程,也许是迄今为止为超导电子开发的最先进的过程,被用作一个例子。该工艺有9个超导层:8个Nb布线层,最小特征尺寸为350 nm,和一个薄的超导层,用于制造紧凑的高动态电感偏置电感器。所有电路层都使用SiO2层间电介质的化学机械平坦化(CMP)完全平坦化。由约瑟夫森结、电路电感器、分流和偏置电阻器等对电路密度施加的物理限制,讨论了超导电路中的能量耗散也进行了审查,以估计是否这种技术,需要低温制冷,可以节能。本文描述了将超导体数字电路的密度提高十倍,并达到每平方厘米约瑟夫森结密度超过10^7的制造工艺发展。

英文摘要:

Superconductor digital electronics using Josephson junctions as ultrafast switches and magnetic-flux encoding of information was proposed over 30 years ago as a sub-terahertz clock frequency alternative to semiconductor electronics based on complementary metal-oxide-semiconductor (CMOS) transistors. Recently, interest in developing superconductor electronics has been renewed due to a search for energy saving solutions in applications related to high-performance computing. The current state of superconductor electronics and fabrication processes are reviewed in order to evaluate whether this electronics is scalable to a very large scale integration (VLSI) required to achieve computation complexities comparable to CMOS processors. A fully planarized process at MIT Lincoln Laboratory, perhaps the most advanced process developed so far for superconductor electronics, is used as an example. The process has nine superconducting layers: eight Nb wiring layers with the minimum feature size of 350 nm, and a thin superconducting layer for making compact high-kinetic-inductance bias inductors. All circuit layers are fully planarized using chemical mechanical planarization (CMP) of SiO2 interlayer dielectric. The physical limitations imposed on the circuit density by Josephson junctions, circuit inductors, shunt and bias resistors, etc., are discussed. Energy dissipation in superconducting circuits is also reviewed in order to estimate whether this technology, which requires cryogenic refrigeration, can be energy efficient. Fabrication process development required for increasing the density of superconductor digital circuits by a factor of ten and achieving densities above 10^7 Josephson junctions per cm^2 is described.

机构、总结、中文摘要均由AI分析而来,可能存在错误,请以论文正文为准。

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