基于紧凑漏电流模型的SRAM单元亚/近阈值时间产额模型
A Timing Yield Model for SRAM Cells in Sub/Near-threshold Voltages Based on A Compact Drain Current Model
摘要:
亚/近阈值静态随机存取存储器(SRAM)设计是解决能量受限应用中存储器瓶颈的关键。然而,高集成度和工艺变化下的可靠性要求非常小的故障概率的准确估计。为了在存储器电路中捕获这样的罕见事件,常规蒙特卡罗(MC)模拟的时间和存储开销是不能容忍的。另一方面,经典的分析方法预测故障概率的物理表达式变得不准确的子/近阈值区域由于假设的分布或过度简化的漏极电流模型的纳米器件。本文首先提出了一个简单有效的漏电流模型来描述低电压下的漏致势垒降低效应。在此基础上,推导了SRAM中兴趣度的概率密度函数。然后提出了两个分析模型来评估SRAM的动态稳定性,包括访问和写时间故障。所提出的模型可以很容易地扩展到不同类型的SRAM与不同的读/写辅助电路。针对不同工作电压和温度下的MC模拟,对模型进行了验证。在0.5VVDD下,对于存取时间和写入失效模型,平均相对误差分别为8.8%和10.4%。所需的数据样本的大小是43.6倍,比国家的最先进的方法。
英文摘要:
Sub/Near-threshold static random-access memory (SRAM) design is crucial for addressing the memory bottleneck in energy-constrained applications. However, the high integration density and reliability under process variations demand an accurate estimation of extremely small failure probabilities. To capture such a rare event in memory circuits, the time and storage overhead of conventional Monte Carlo (MC) simulations cannot be tolerated. On the other hand, classic analytical methods predicting failure probabilities from a physical expression become inaccurate in the sub/near-threshold region due to the assumed distribution or the oversimplified drain current model for nanoscale devices. This work first proposes a simple but efficient drain current model to describe the drain-induced barrier lowering effect at low voltages. Based on that, the probability density functions of the interest metrics in SRAM are derived. Two analytical models are then put forward to evaluate SRAM dynamic stabilities including access and write-time failures. The proposed models can be extended easily to different types of SRAM with different read/write assist circuits. The models are validated against MC simulations across different operating voltages and temperatures. The average relative errors at 0.5V VDD are only 8.8% and 10.4% for the access-time and write failure models respectively. The size of required data samples is 43.6X smaller than that of the state-of-the-art method.
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