AI 中文总结
该研究提出一款面向2nm节点的工艺感知混合Si/IGO单片3D 6T SRAM，通过新颖的邻胞共享源漏位线设计实现面积缩减，相比硅基准单元在静态噪声容限、写入延迟及能量延迟积上均有优化。
AI 中文摘要
我们提出了一种面向2nm节点的单片3D（M3D）6T SRAM，其集成了后端制程（BEOL）IGO传输门（PG）、全硅纳米片锁存器、掩埋电源轨（BPR）以及Ru互连。将针对最先进的双栅IGO晶体管校准的TCAD与三层HfO₂/ZrO₂/HfO₂（HZH）栅叠层技术，结合虚拟制造和3D寄生参数提取，实现了该拓扑的首个工艺感知版图。一种新颖的邻胞共享源漏（S/D）位线（BL）设计扩大了IGO接触面积，以缓解接触电阻并在不损失面积的情况下恢复传输门驱动能力。该单元相比高性能（HP）122硅基准单元实现了25%的面积缩减，同时在宽电源电压范围内保持了稳健的静态噪声容限（SNM）。在128×256子阵列级别，由于面积缩小带来的单元寄生参数和字线（WL）负载降低，相比高密度（HD）111硅基准单元，其写入延迟降低了42.2%，能量延迟积（EDP）降低了9.7%。
英文摘要
We propose a monolithic-3D (M3D) 6T SRAM at the 2nm node, integrating BEOL IGO pass-gates (PGs) with an all-silicon nanosheet latch, buried power rails (BPRs), and Ru interconnects. TCAD calibrated to a state-of-the-art double-gate IGO transistor with a tri-layer HfO$_2$/ZrO$_2$/HfO$_2$ (HZH) gate stack is combined with virtual fabrication and 3D parasitic extraction to realize the first process-aware layout of this topology. A novel neighbor-cell shared source/drain (S/D) bitline (BL) design enlarges the IGO contact area to mitigate contact resistance and restore PG drive without area penalty. The resulting cell achieves a 25\% footprint reduction vs the high-performance (HP) 122 Si baseline while maintaining robust static noise margin (SNM) over a wide supply voltage range. At the 128$\times$256 subarray-level, it reduces write delay by 42.2\% and EDP by 9.7\% compared to the high-density (HD) 111 Si baseline, owing to reduced cell parasitics and wordline (WL) loading from the smaller footprint.
