This paper reports on the development of a resource-efficient FPGA-based neural network regression model for potential applications in the future hardware muon trigger system of the ATLAS experiment at the Large Hadron Collider (LHC). Effective real-time selection of muon candidates is the cornerstone of the ATLAS physics programme. With the planned ATLAS upgrades for the High Luminosity LHC, an entirely new FPGA-based hardware muon trigger system will be installed that will process full muon detector data within a 10 $μs$ latency window. The large FPGA devices planned for this upgrade should have sufficient spare resources to allow deployment of machine learning methods for improving identification of muon candidates and searching for new exotic particles. Our neural network regression model promises to improve rejection of the dominant source of background trigger events in the central detector region, which are due to muon candidates with low transverse momenta. This model was implemented in FPGA using 157 digital signal processors and about 5,000 lookup tables. The simulated network latency and deadtime are 122 and 25 ns, respectively, when implemented in the FPGA device using a 320 MHz clock frequency. Two other FPGA implementations were also developed to study the impact of design choices on resource utilisation and latency. The performance parameters of our FPGA implementation are well within the requirements of the future muon trigger system, therefore opening a possibility for deploying machine learning methods for future data taking by the ATLAS experiment.
We propose a new fixed latency scheme for Xilinx gigabit transceivers that will be used in the upgrade of the ATLAS forward muon spectrometer at the Large Hadron Collider. The fixed latency scheme is implemented in a 4.8 Gbps link between a frontend data serializer ASIC and a packet router. To achieve fixed latency, we use IO delay and dedicated carry in resources in a Xilinx FPGA, while minimally relying on the embedded features of the FPGA transceivers. The scheme is protocol independent and can be adapted to FPGA from other vendors with similar resources. This paper presents a detailed impl…
We present a multi-layer single-event upset mitigation strategy implemented in a low-cost Xilinx Artix-7 FPGA. The implementation is targeted for a trigger data router for the ATLAS muon spectrometer upgrade. The mitigation strategy employs three layers of protection to improve overall FPGA design robustness: use of triple-modular redundancy for FPGA fabric logic and embedded soft-error mitigation in the first layer; further enhancement with multi-boot FPGA reconfiguration across multiple copies of configuration memory in the second layer; and FPGA power cycling and configuration memory re-ini…
This paper presents a readout system designed for testing the prototype of Small-Strip Thin Gap Chamber (sTGC), which is one of the main detector technologies used for ATLAS New-Small-Wheel Upgrade. This readout system aims at testing one full-size sTGC quadruplet with cosmic muon triggers.
The ATLAS experiment pixel detector upgrade plans are focused on development of new technology, including the FE-I4 readout integrated circuit. The first upgrade project to make use of this new technology is an "Insertable B-Layer" (IBL) pixel detector to be installed on a replacement beam pipe in 2013. The IBL will fit inside and not alter the existing ATLAS pixel detector. However, the possibility is being studied to replace the pixel whole detector in 2018 with a lower mass, higher performance instrument based on the FE-I4 chip and new mechanical structures.
The ATLAS detector has to undergo significant updates at the end of the current decade, in order to withstand the increased occupancy and radiation damage that will be produced by the high-luminosity upgrade of the Large Hadron Collider. In this presentation we give an overview of the recent accomplishments of the R&D activity on the planar pixel sensors for the ATLAS Inner Detector upgrade.
The LHC is expected to reach luminosities up to 3000fb-1 and the innermost layer of the ATLAS upgrade plans to cope with higher occupancy and to decrease the pixel size. 3D-Si sensors are a good candidate for the innermost layer of the ATLAS pixel upgrade since they exhibit good performance under high fluences and the new designs will have smaller pixel size to fulfill the electronics expectations. This paper reports TCAD simulations of the 3D-Si sensors designed at IMB-CNM with non passing-through columns that are being fabricated for the next innermost layer of the ATLAS pixel upgrade, shows…
We present an FPGA-based readout chip emulator board for the CMS Endcap Timing Layer (ETL) detector upgrade. The emulator board uses an Intel Cyclone 10 GX FPGA to emulate the digital functions of four Endcap Layer Readout Chips (ETROCs). Based on the actual ETROC design, the firmware is implemented and verified. The emulator board is being used for the ETROC digital design verification and system development.
Following the Higgs particle discovery, the Large Hadron Collider complex will be upgraded in several phases allowing the luminosity to increase to $7 \times 10^{34}cm^{-2}s^{-1}$. In order to adapt the ATLAS detector to the higher luminosity environment after the upgrade, part of the ATLAS muon end-cap system, the Small Wheel, will be replaced by the New Small Wheel. The New Small Wheel includes two kinds of detectors: small-strip Thin Gap Chambers and Micromegas. Shandong University, part of the ATLAS collaboration, participates in the construction of the ATLAS New Small Wheel by developing,…
The innermost station of the present ATLAS forward muon detector needs to be upgraded for the super-LHC. We present a proposal to replace it with a sandwiched detector composed of several layers of small-radius Monitored Drift Tube chambers (sMDT) for precision tracking measurement and two stations of multi-gap Resistive Plate Chambers (mRPC) for triggering purpose. We describe the layout of the upgraded detector and the trigger strategy. Several modifications to the RPCs used in the ATLAS barrel region are needed to satisfy the super-LHC requirements. Various studies with the proposed mRPC ti…
The Large Hadron Collider (LHC) has been successfully delivering proton-proton collision data at the unprecedented center of mass energy of 13 TeV. An upgrade is planned to increase the instantaneous luminosity delivered by the LHC in what is called the HL-LHC, aiming to deliver a total of up 3000 fb$^{-1}$ to 4000 fb$^{-1}$ of data per experiment. To cope with the expected data-taking conditions ATLAS is planning upgrades of the detector. Six Technical Design Reports (TDR) were produced by the ATLAS Collaboration. In these TDRs the physics motivation and benefits of such upgrades are discusse…
After the successful LHC operation at the center-of-mass energies of 7 and 8 TeV in 2010-2012, plans are actively advancing for a series of upgrades of the accelerator, culminating roughly ten years from now in the high-luminosity LHC (HL-LHC) project, delivering of the order of five times the LHC nominal instantaneous luminosity along with luminosity leveling. The final goal is to extend the dataset from about few hundred fb$^{-1}$ to 3000 fb$^{-1}$ by around 2035 for ATLAS and CMS. In parallel, the experiments need to be kept lockstep with the accelerator to accommodate running beyond the no…
Calibration of the discriminator threshold of the Amplifier-Shaper-Discriminator Chip for the Upgrade of the ATLAS Muon Drift-Tube Chambers for the High-Luminosity LHC
Micromegas is one of the detector technologies (along with the small Thin Gap Chambers) that has been chosen for precision tracking and triggering purposes of the ATLAS muon forward detectors in the view of LHC luminosity increase. To fulfill the requirements of such upgrade, several prototype micromegas detectors were tested in recent test beam campaigns with high energy hadron beams at CERN. Performance studies and results on spatial resolution for perpendicular and inclined tracks, efficiency, as well detector performance and comparison to simulation in a magnetic field are presented. Moreo…
With the LHC successfully collecting data at 7 TeV, plans are actively advancing for a series of upgrades leading eventually to about five times the LHC design-luminosity some 10-years from now in the High-Luminosity LHC (HL-LHC) project. Coping with the high instantaneous and integrated luminosity will require many changes to the ATLAS detector. The designs are developing rapidly for an all-new inner-tracker, significant changes in the calorimeter and muon systems, as well as improved triggers. This article summarizes the environment expected at the HL-LHC and the status of various improvemen…
The instantaneous luminosity of the Large Hadron Collider at CERN will be increased by up to a factor of five to seven with respect to the design value. To maintain an excellent detection and background rejection capability in the forward region of the ATLAS detector, part of the muon detection system will be upgraded during LHC shutdown periods with the replacement of part of the present first station in the forward regions with the so-called New Small Wheels (NSWs). The NSWs will have a diameter of approximately 10 m and will be made of two detector technologies: Micromegas and small-strip T…
The ATLAS experiment at CERN measures energy of proton-proton (p-p) collisions with a repetition frequency of 40 MHz at the Large Hadron Collider (LHC). The readout electronics of liquid-argon (LAr) calorimeters are being prepared for high luminosity-LHC (HL-LHC) operation as part of the phase-II upgrade, anticipating a pileup of up to 200 simultaneous p-p interactions. The increase of the number of p-p interactions implies that calorimeter signals of up to 25 consecutive collisions overlap, making energy reconstruction more challenging. In order to achieve the goal of the HL-HLC, field-progra…
Small-diameter Muon Drift Tube (sMDT) chambers have been developed for the ATLAS muon detector upgrade. They possess an improved rate capability and a more compact design with respect to the existing chambers, which allows to equip detector regions uninstrument at present. The chamber assembly methods have been optimized for mass production, while the sense wire positioning accuracy is improved to below ten microns. The chambers will be ready for installation in the winter shutdown 2016/17 of the Large Hadron Collider. The design and construction of the new sMDT chambers for ATLAS will be disc…
After the first successful LHC run in 2010-2012, plans are actively advancing for a series of upgrades leading eventually to about above times the design-luminosity in about ten years. The larger luminosity will allow to perform precise measurements of the just discovered Higgs boson and to continue searching for new physics beyond the Standard Model. Coping with the high instantaneous and integrated luminosity will be a great challenge for the ATLAS detector and will require changes in most of the subsystems, specially those at low radii and large pseudorapidity, as well as in its trigger arc…
A radiation-hard quad-channel 12-bit 40 MSPS pipeline analog-to-digital converter (ADC) has been designed for the trigger readout electronics Phase-I upgrade of the ATLAS Liquid Argon calorimeter, at the CERN Large Hadron Collider. The final version of the custom design, fabricated in a commercial 130 nm CMOS process, is presented and found to meet the system requirements for analog performance and radiation tolerance. The procedure for quality control of 17200 ADCs is described and the results are presented.
The ATLAS Planar Pixel Sensor R&D Project is a collaboration of 17 institutes and more than 80 scientists. Their goal is to explore the operation of planar pixel sensors for the tracker upgrade at the High Luminosity-Large Hadron Collider (HL-LHC). This work will give a summary of the achievements on radiation studies with n-in-n and n-in-p pixel sensors, bump-bonded to ATLAS FE-I3 and FE-I4 readout chips. The summary includes results from tests with radioactive sources and tracking efficiencies extracted from test beam measurements. Analysis results of ${2\cdot10^{16}} \text{n}_{\text{eq}}\te…
For Run 3 (from 2021), the LHC will undergo a significant increase in instantaneous luminosity to 1.5 times its current value which will lead to larger collected statistics and an enhanced sensitivity to new physics. The Phase-1 upgrade of the ATLAS Level-1 endcap muon trigger is essential to keep the physics acceptance at Run 3. A new trigger logic to take coincidence with detectors inside and outside the magnetic field is described and is shown to reduce the trigger rate to lower than the required level in Run 3. A new trigger board, NSL, to integrate all the information from various detecto…
A completely New Small Wheel (NSW) will be constructed for ATLAS Phase-1 upgrade. Small-Strip Thin-Gap-Chamber (sTGC) will devote to the trigger function of NSW. A full-size sTGC quadruplet consists of 4 layers, and will need 4 pad Front-End-Boards and 4 strip Front-End-Boards for sTGC signals readout. The 8 boards should be readout simultaneously at a time. This paper presents the study of multi-layer sTGC test system, a FEB Driver Card (FEBDC) is designed for pFEB and sFEB boards handling. The design and test of FEBDC are described in details.
The Phase-II upgrade of the ATLAS detector for the High Luminosity Large Hadron Collider (HL-LHC) includes the replacement of the current Inner Detector with an all-silicon tracker consisting of pixel and strip detectors. The current Phase-II detector layout requires the construction of 20,000 strip detector modules consisting of sensor, circuit boards and readout chips, which are connected mechanically using adhesives. The adhesive between readout chips and circuit board is a silver epoxy glue as was used in the current ATLAS SemiConductor Tracker (SCT). This glue has several disadvantages, w…
Planned upgrades of the LHC over the next decade should allow the machine to operate at a center of mass energy of 14 TeV with instantaneous luminosities in the range 5--7e34 cm^-2 s^-1. With these parameters, ATLAS could collect 3,000 fb^-1 of data in approximately 10 years. However, the conditions under which this data would be acquired are much harsher than those currently encountered at the LHC. For example, the number of proton-proton interactions per bunch crossing will rise from the level of 20--30 per 50 ns crossing observed in 2012 to 140--200 every 25 ns. In order to deepen our under…
The ATLAS detector is set to undergo a substantial upgrade termed the "Phase-II" upgrade during the Long-Shutdown in preparation for the start of operation of the High Luminosity Large Hadron Collider (HL-LHC). This paper describes the development and implementation of the Phase-II upgrade low voltage power supply transformer-coupled buck converter (Brick) test bench. A large scale production of approximately 2048 finger low voltage power supplies, with an identical output voltage, is set to be undertaken in the year 2022. This production will culminate in the complete replacement of the LVPS …
A wealth of physics results have already been obtained from the LHC, due to the excellent performance of the collider and its experiments. Even more results are expected to be achievable in the phase of the high-luminosity LHC (HL-LHC). It is foreseen to deliver a ten times higher LHC design luminosity resulting in about 4000 fb-1 within ten years of operation. The upgrade of the LHC is driven by the prospect to observe and measure rare processes. High particle production rates and radiation doses result in a challenging environment for the collider experiments. The ATLAS and CMS experiments a…
ATLAS-SCT has developed a new ATLAS trigger card, 'Digital Atlas Vme Electronics' ("DAVE"). The unit is designed to provide a versatile array of interface and logic resources, including a large FPGA. It interfaces to both VME bus and USB hosts. DAVE aims to provide exact ATLAS CTP (ATLAS Central Trigger Processor) functionality, with random trigger, simple and complex deadtime, ECR (Event Counter Reset), BCR (Bunch Counter Reset) etc. being generated to give exactly the same conditions in standalone running as experienced in combined runs. DAVE provides additional hardware and a large amount o…
The PreProcessor of the ATLAS Level-1 Calorimeter Trigger prepares the analogue trigger signals sent from the ATLAS calorimeters by digitising, synchronising, and calibrating them to reconstruct transverse energy deposits, which are then used in further processing to identify event features. During the first long shutdown of the LHC from 2013 to 2014, the central components of the PreProcessor, the Multichip Modules, were replaced by upgraded versions that feature modern ADC and FPGA technology to ensure optimal performance in the high pile-up environment of LHC Run 2. This paper describes the…
In view of the LHC upgrade phases towards the High Luminosity LHC (HL-LHC), the ATLAS experiment plans to upgrade the Inner Detector with an all-silicon system. The n-on-p silicon technology is a promising candidate to achieve a large area instrumented with pixel sensors, since it is radiation hard and cost effective. The paper reports on the performance of novel n-on-p edgeless planar pixel sensors produced by FBK-CMM, making use of the active trench for the reduction of the dead area at the periphery of the device. After discussing the sensor technology an overview of the first beam test res…
In view of the LHC upgrade phases towards HL-LHC, the ATLAS experiment plans to upgrade the Inner Detector with an all-silicon system. The n-on-p silicon technology is a promising candidate for the pixel upgrade thanks to its radiation hardness and cost effectiveness, that allow for enlarging the area instrumented with pixel detectors. We report on the development of novel n-in-p edgeless planar pixel sensors fabricated at FBK (Trento, Italy), making use of the "active edge" concept for the reduction of the dead area at the periphery of the device. After discussing the sensor technology and fa…
This paper describes the integration structures for the silicon strips tracker of the ATLAS detector proposed for the Phase-II upgrade of the Large Hadron Collider (LHC), also referred to as High Luminosity LHC (HL-LHC). In this proposed detector Silicon strip sensors are arranged in highly modular structures, called `staves' and `petals'. This paper presents performance results from the latest prototype stave built at Berkeley. This new, double-sided prototype is composed of a specialized core structure, in which a shield-less bus tape is embedded in between carbon fiber lay-ups. A detailed d…
In view of the LHC upgrade phases towards the High Luminosity LHC (HL-LHC), the ATLAS experiment plans to upgrade the Inner Detector with an all-silicon system. Because of its radiation hardness and cost effectiveness, the n-on-p silicon technology is a promising candidate for a large area pixel detector. The paper reports on the joint development, by LPNHE and FBK of novel n-on-p edgeless planar pixel sensors, making use of the active trench concept for the reduction of the dead area at the periphery of the device. After discussing the sensor technology, and presenting some sensors' simulatio…
The LHC Phase-II upgrade will lead to a significant increase in luminosity, which in turn will bring new challenges for the operation of inner tracking detectors. A possible solution is to use active silicon sensors, taking advantage of commercial CMOS technologies. Currently ATLAS R&D programme is qualifying a few commercial technologies in terms of suitability for this task. In this paper a prototype designed in one of them (LFoundry 150 nm process) will be discussed. The chip architecture will be described, including different pixel types incorporated into the design, followed by simulation…
An optical link system is being developed for the ATLAS Liquid Argon Calorimeter Phase-II upgrade. The optical link system is responsible for transmit the data of over 182 thousand detector channels from 1524 Front-End Boards (FEBs) through 26 optical fibers per FEB over 150 meters to the counting room and brings clocks, bunch crossing reset signals and slow control/monitoring signals back to the FEBs. The optical link system is based on the Low-Power GigaBit Transceivers (lpGBTs) and the Versatile optical Transceiver (VTRx+) modules, which both are being developed for the High-Luminosity LHC …
ATLAS detector at the LHC will undergo a major Phase-II upgrade for the High Luminosity LHC. The upgrade affects all major ATLAS systems, including the Trigger and Data Acquisition systems. As part of the Level-0 Trigger System, the Global Trigger uses full-granularity calorimeter cells to perform algorithms, refines the trigger objects and applies topological requirements. The Global Trigger uses a Global Common Module as the building block of its design. To achieve a high input and output bandwidth and substantial processing power, the Global Common Module will host the most advanced FPGAs a…
In view of the LHC upgrade for the High Luminosity Phase (HL-LHC), the ATLAS experiment is planning to replace the Inner Detector with an all-Silicon system. The n-on-p technology represents a valid solution for the modules of most of the layers, given the significant radiation hardness of this option and the reduced cost. There is also the demand to reduce the inactive areas to a minimum. The ATLAS LPNHE Paris group and FBK Trento started a collaboration for the development on a novel n-on-p edgeless planar pixel design, based on the deep-trench process which can cope with all these demands. …
The Tile Calorimeter (TileCal) is the hadronic calorimeter covering the most central region of the ATLAS experiment at LHC. The TileCal readout consists of about 10000 channels. The ATLAS upgrade program is divided in three phases: The Phase~0 occurs during 2013-2014, Phase~1 during 2018-1019 and finally Phase~2, which is foreseen for 2022-2023, whereafter the peak luminosity will reach 5-7 x 10$^{34}$ cm$^2$s$^{-1}$ (HL-LHC). The main TileCal upgrade is focused on the Phase~2 period. The upgrade aims at replacing the majority of the on- and off-detector electronics so that all calorimeter sig…
This work presents a depleted monolithic active pixel sensor (DMAPS) prototype manufactured in the LFoundry 150 nm CMOS process. The described device, named LF-Monopix, was designed as a proof of concept of a fully monolithic sensor capable of operating in the environment of outer layers of the ATLAS Inner Tracker upgrade for the High Luminosity Large Hadron Collider (HL-LHC). Implementing such a device in the detector module will result in a lower production cost and lower material budget compared to the presently used hybrid designs. In this paper the chip architecture will be described foll…
The expected increase of total integrated luminosity by a factor of ten at the HL-LHC compared to the design goals for LHC essentially eliminates the safety factor for radiation hardness realized at the current cold amplifiers of the ATLAS Hadronic Endcap Calorimeter (HEC). New more radiation hard technologies have been studied: SiGe bipolar, Si CMOS FET and GaAs FET transistors have been irradiated with neutrons up to an integrated fluence of 2.2 \cdot 10^{16} n/cm2 and with 200 MeV protons up to an integrated fluence of 2.6 \cdot 10^{14} p/cm2. Comparisons of transistor parameters such as th…
In the framework of the HL-LHC upgrade, the ATLAS experiment plans to introduce an all-silicon inner tracker to cope with the elevated occupancy. To investigate the suitability of pixel sensors using the proven planar technology for the upgraded tracker, the ATLAS Planar Pixel Sensor R&D Project (PPS) was established comprising 19 institutes and more than 90 scientists. The paper provides an overview of the research and development project and highlights accomplishments, among them: beam test results with planar sensors up to innermost layer fluences (> 10^16 n_eq cm^2); measurements obtained …
In view of the LHC upgrade phases towards the High Luminosity LHC (HL-LHC), the ATLAS experiment plans to upgrade the Inner Detector with an all-silicon system. Because of its radiation hardness and cost effectiveness, the n-on-p silicon technology is a promising candidate for a large area pixel detector. The paper reports on the joint development, by LPNHE and FBK of novel n-on-p edgeless planar pixel sensors, making use of the active trench concept for the reduction of the dead area at the periphery of the device. After discussing the sensor technology, a complete overview of the electrical …
The Tile Calorimeter at ATLAS is a hadron calorimeter based on steel plates and scintillating tiles read out by PMTs. The current read-out system uses standard ADCs and custom ASICs to digitize and temporarily store the data on the detector. However, only a subset of the data is actually read out to the counting room. The on-detector electronics will be replaced around 2023. To achieve the required reliability the upgraded system will be highly redundant. Here the ASICs will be replaced with Kintex-7 FPGAs from Xilinx. This, in addition to the use of multiple 10 Gbps optical read-out links, wi…
With half the drift-tube diameter of the Monitored Drift Tube (MDT) chambers of the ATLAS muon spectrometer and otherwise unchanged operating parameters, small-diameter Muon Drift Tube (sMDT) chambers provide an order of magnitude higher rate capability and can be installed in detector regions where MDT chambers do not fit. The chamber assembly time has been reduced by a factor of seven to one working day and the sense wire positioning accuracy improved by a factor of two to better than ten microns. Two sMDT chambers have been installed in ATLAS in 2014 to improve the momentum resolution in th…
We report on the design of a serializer ASIC to be used in the ATLAS forward muon detector for trigger data transmission. We discuss the performance of a prototype chip covering power dissipation, latency and stable operating line rate. Tests show that the serializer is capable of running at least at 5.76 Gbps with a bit error ratio below 1x10^{-15}, and a power consumption of 200 mW running at 4.8 Gbps. The latency between the start of loading 30 bits into the serializer to the transmission of the first bit from the serializer is measured to be about 6 ns.
The design of a radiation-hard dual channel 12-bit 40 MS/s pipeline ADC with extended dynamic range is presented, for use in the readout electronics upgrade for the ATLAS Liquid Argon Calorimeters at the CERN Large Hadron Collider. The design consists of two pipeline A/D channels with four Multiplying Digital-to-Analog Converters with nominal 12-bit resolution each. The design, fabricated in the IBM 130 nm CMOS process, shows a performance of 68 dB SNDR at 18 MHz for a single channel at 40 MS/s while consuming 55 mW/channel from a 2.5 V supply, and exhibits no performance degradation after irr…
The LHC upgrade is planned to enhance the instantaneous luminosity during Run 3 from 2021 through 2023. The Phase-I upgrade of the trigger readout electronics for the ATLAS Liquid Argon (LAr) Calorimeters will be installed during the second long shutdown of LHC in 2019-2020. In this upgrade, the so-called super cells are introduced to provide higher granularity, higher resolution and longitudinal shower shape information from the LAr calorimeters to the level-1 trigger processors. A new LAr Trigger Digitizer Board (LTDB) will manipulate and digitize 320 channels of super cell signals, and tran…
A new Muon-to-Central-Trigger Processor Interface (MUCTPI) was built as part of the upgrade of the ATLAS Level-1 trigger system for the next Run of the Large Hadron Collider at CERN. The MUCTPI has 208 high-speed optical serial links for receiving muon candidates from the muon trigger detectors. Three high-end FPGAs are used for real-time processing of the muon candidates, for sending trigger information to other parts of the trigger system, and for sending summary information to the data acquisition and monitoring system. A System-on-Chip (SoC) is used for the control, configuration and monit…
The expected increase of total integrated luminosity by a factor ten at the HL-LHC compared to the design goals for LHC essentially eliminates the safety factor for radiation hardness realized at the current cold amplifiers of the ATLAS Hadronic End-cap Calorimeter (HEC). New more radiation hard technologies have been studied: SiGe bipolar, Si CMOS FET and GaAs FET transistors have been irradiated with neutrons up to an integrated fluence of 2.2 x 10^{16} n/cm^2 and with 200 MeV protons up to an integrated fluence of 2.6 x 10^{14} p/cm^2. Comparisons of transistor parameters such as the gain f…
Results of beam tests with planar silicon pixel sensors aimed towards the ATLAS Insertable B-Layer and High Luminosity LHC (HL-LHC) upgrades are presented. Measurements include spatial resolution, charge collection performance and charge sharing between neighbouring cells as a function of track incidence angle for different bulk materials. Measurements of n-in-n pixel sensors are presented as a function of fluence for different irradiations. Furthermore p-type silicon sensors from several vendors with slightly differing layouts were tested. All tested sensors were connected by bump-bonding to …
The challenging demands of the ATLAS High Luminosity (HL-LHC) Upgrade aim for a complete swap of new generation sensors that should cope with the ultimate radiation hardness. FBK has been one of the prime foundries to develop and fabricate such radiation-hard 3D silicon (Si) sensors. These sensors are chosen to be deployed into the innermost layer of the ATLAS Inner Tracker (ITk). Recently, a pre-production batch of 3D Si sensors of 50x50 um2 pixel geometry, compatible with the full-size ITKPix (RD53B) readout chip, was fabricated. Two wafers holding temporary metal were diced at IZM, Germany,…
Electron and photon triggers covering transverse energies from 5 GeV to several TeV are essential for signal selection in a wide variety of ATLAS physics analyses to study Standard Model processes and to search for new phenomena. Final states including leptons and photons had, for example, an important role in the discovery and measurement of the Higgs particle. Dedicated triggers are also used to collect data for calibration, efficiency and fake rate measurements. The ATLAS trigger system is divided in a hardware-based (Level 1) and a software based High-Level Trigger (HLT), both of which wer…
This paper describes the small-diameter monitored drift-tube detector construction at the University of Michigan as a contribution to the ATLAS Muon Spectrometer upgrade for the high-luminosity Large Hadron Collider at CERN. Measurements of the first 30 chambers built at Michigan show that the drift tube wire position accuracy meets the specification of 20 microns. The positions of the platforms for alignment and magnetic field sensors are all installed well within the required precision. The cosmic ray test measurements show single wire tracking resolution of 100 +- 7 microns with an average …
High Voltage CMOS sensors are a promising technology for tracking detectors in collider experiments. Extensive R&D studies are being carried out by the ATLAS Collaboration for a possible use of HV-CMOS in the High Luminosity LHC upgrade of the Inner Tracker detector. CaRIBOu (Control and Readout Itk BOard) is a modular test system developed to test Silicon based detectors. It currently includes five custom designed boards, a Xilinx ZC706 development board, FELIX (Front-End LInk eXchange) PCIe card and a host computer. A software program has been developed in Python to control the CaRIBOu hardw…
Silicon detectors based on the HV-CMOS technology are being investigated as possible candidate for the outer layers of the ATLAS pixel detector for the High Luminosity LHC. In this framework the H35Demo ASIC has been produced in the 350 nm AMS technology (H35). The H35Demo chip has a large area ($18.49 \times 24.40 \, \mathrm{mm^2}$) and includes four different pixel matrices and three test structures. In this paper the radiation hardness properties, in particular the evolution of the depletion region with fluence is studied using edge-TCT on test structures. Measurements on the test structure…
ATLAS is making extensive efforts towards preparing a detector upgrade for the high luminosity operations of the LHC (HL-LHC), which will commence operation in about 10 years. The current ATLAS Inner Detector will be replaced by an all-silicon tracker (comprising an inner Pixel tracker and outer Strip tracker). The software currently used for the new silicon tracker is broadly inherited from that used for the LHC Run-1 and Run-2, but many new developments have been made to better fulfill the future detector and operation requirements. One aspect in particular which will be highlighted is the s…
