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arXiv 2109.12239cs.ITeess.SPmath.IT
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极化码的快速逐次消去列表翻转译码

Fast Successive-Cancellation List Flip Decoding of Polar Codes

Nghia Doan, Seyyed Ali Hashemi, Warren J. Gross

摘要:

本工作提出了一种用于极化码的快速连续消除列表翻转(Fast-SCLF)解码算法,其解决了与连续消除列表翻转(SCLF)解码算法相关联的高延迟问题。首先,我们提出了一个比特翻转策略,适合于最先进的快速连续取消列表(FSCL)解码,避免了SCLF的二叉树表示中的树遍历,从而减少了解码过程的延迟。然后,我们推导出一个参数化的路径选择误差模型,以准确地估计从初始FSCL解码中消除正确解码路径的位索引。基于有效的监督学习框架在线优化可训练参数。仿真结果表明,对于具有256个信息比特的长度为512的极化码,在具有相似的纠错性能和存储器消耗的情况下,所提出的Fast-SCLF解码器在$10^{-4}$的误出错率下将具有相同列表大小的SCLF解码器的平均解码延迟减少多达$73.4\%$,同时引起$27.6\%$的最大计算复杂性度开销。对于具有256个信息比特的长度为512的相同极化码并且在实际信噪比下,所提出的具有列表大小4的解码器分别降低了具有列表大小32的FSCL解码器(FSCL-32)的平均复杂度和解码延迟的$89.3\%$和$43.7\%$,同时还降低了FSCL-32的存储器消耗的$83.2\%$。与FSCL-32相比,所提出的解码器的显著改进是以$0.07$ dB纠错性能下降为代价的。

英文摘要:

This work presents a fast successive-cancellation list flip (Fast-SCLF) decoding algorithm for polar codes that addresses the high latency issue associated with the successive-cancellation list flip (SCLF) decoding algorithm. We first propose a bit-flipping strategy tailored to the state-of-the-art fast successive-cancellation list (FSCL) decoding that avoids tree-traversal in the binary tree representation of SCLF, thus reducing the latency of the decoding process. We then derive a parameterized path selection error model to accurately estimate the bit index at which the correct decoding path is eliminated from the initial FSCL decoding. The trainable parameter is optimized online based on an efficient supervised learning framework. Simulation results show that for a polar code of length 512 with 256 information bits, with similar error-correction performance and memory consumption, the proposed Fast-SCLF decoder reduces up to $73.4\%$ of the average decoding latency of the SCLF decoder with the same list size at the frame error rate of $10^{-4}$, while incurring a maximum computational complexity overhead of $27.6\%$. For the same polar code of length 512 with 256 information bits and at practical signal-to-noise ratios, the proposed decoder with list size 4 reduces $89.3\%$ and $43.7\%$ of the average complexity and decoding latency of the FSCL decoder with list size 32 (FSCL-32), respectively, while also reducing $83.2\%$ of the memory consumption of FSCL-32. The significant improvements of the proposed decoder come at the cost of $0.07$ dB error-correction performance degradation compared with FSCL-32.

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