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arXiv 1306.3529cs.ITmath.IT

Scalable Successive-Cancellation Hardware Decoder for Polar Codes

Alexandre J. Raymond, Warren J. Gross

英文摘要:

Polar codes, discovered by Arıkan, are the first error-correcting codes with an explicit construction to provably achieve channel capacity, asymptotically. However, their error-correction performance at finite lengths tends to be lower than existing capacity-approaching schemes. Using the successive-cancellation algorithm, polar decoders can be designed for very long codes, with low hardware complexity, leveraging the regular structure of such codes. We present an architecture and an implementation of a scalable hardware decoder based on this algorithm. This design is shown to scale to code lengths of up to N = 2^20 on an Altera Stratix IV FPGA, limited almost exclusively by the amount of available SRAM.

机构、总结、中文摘要均由AI分析而来,可能存在错误,请以论文正文为准。

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