面向可扩展应用级后硅封装的特征工程
Feature Engineering for Scalable Application-Level Post-Silicon Debugging
摘要：
我们提出了系统和有效的解决方案，可观察性增强和根本原因诊断后硅系统芯片（SoC）验证与不同的使用场景。我们在典型的应用程序中的消息选择模型规范的交互流。我们的消息选择方法优化了流规范覆盖率和跟踪缓冲区利用率。我们将诊断问题定义为将有缺陷的痕迹识别为离群值，将无缺陷的痕迹识别为内点/正常行为，为此我们使用无监督学习算法进行离群值检测。我们使用特征工程来将原始特征转换为使用域特定操作的更复杂的特征，而不是使用信号作为原始特征在跟踪数据上直接应用机器学习算法。工程特性与诊断任务高度相关，并且通用于任何硬件设计。我们目前的调试和根本原因分析的微妙的硅后的错误在工业规模的OpenCRT 2 SoC。我们实现了跟踪缓冲区的利用率为98.96%的流规范覆盖率为94.3%（平均）。与人工调试相比，该诊断方法能够多诊断出66.7%的错误，诊断时间减少了847 $\times$，诊断精度为0.769。
英文摘要：
We present systematic and efficient solutions for both observability enhancement and root-cause diagnosis of post-silicon System-on-Chips (SoCs) validation with diverse usage scenarios. We model specification of interacting flows in typical applications for message selection. Our method for message selection optimizes flow specification coverage and trace buffer utilization. We define the diagnosis problem as identifying buggy traces as outliers and bug-free traces as inliers/normal behaviors, for which we use unsupervised learning algorithms for outlier detection. Instead of direct application of machine learning algorithms over trace data using the signals as raw features, we use feature engineering to transform raw features into more sophisticated features using domain specific operations. The engineered features are highly relevant to the diagnosis task and are generic to be applied across any hardware designs. We present debugging and root cause analysis of subtle post-silicon bugs in industry-scale OpenSPARC T2 SoC. We achieve a trace buffer utilization of 98.96\% with a flow specification coverage of 94.3\% (average). Our diagnosis method was able to diagnose up to 66.7\% more bugs and took up to 847$\times$ less diagnosis time as compared to the manual debugging with a diagnosis precision of 0.769.
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