Room-temperature Fermi-Dirac electron thermal excitation in conventional three-dimensional (3D) or two-dimensional (2D) semiconductors generates hot electrons with a relatively long thermal tail in energy distribution. These hot electrons set a fundamental obstacle known as the "Boltzmann tyranny" that limits the subthreshold swing (SS) and therefore the minimum power consumption of 3D and 2D field-effect transistors (FETs). Here, we investigated a novel graphene (Gr)-enabled cold electron injection where the Gr acts as the Dirac source to provide the cold electrons with a localized electron density distribution and a short thermal tail at room temperature. These cold electrons correspond to an electronic cooling effect with the effective electron temperature of ~145 K in the monolayer MoS2, which enable the transport factor lowering and thus the steep-slope switching (across for 3 decades with a minimum SS of 29 mV/decade at room temperature) for a monolayer MoS2 FET. Especially, a record-high sub-60-mV/decade current density (over 1 μA/μm) can be achieved compared to conventional steep-slope technologies such as tunneling FETs or negative capacitance FETs using 2D or 3D channel materials. Our work demonstrates the great potential of 2D Dirac-source cold electron transistor as an innovative steep-slope transistor concept, and provides new opportunities for 2D materials toward future energy-efficient nanoelectronics.
Steep-slope $β$-Ga$_2$O$_3$ nano-membrane negative capacitance field-effect transistors (NC-FETs) are demonstrated with ferroelectric hafnium zirconium oxide in gate dielectric stack. Subthreshold slope less than 60 mV/dec at room temperature is obtained for both forward and reverse gate voltage sweeps with a minimum value of 34.3 mV/dec at reverse gate voltage sweep and 53.1 mV/dec at forward gate voltage sweep at $V_{DS}$=0.5 V. Enhancement-mode operation with threshold voltage ~0.4 V is achieved by tuning the thickness of $β$-Ga$_2$O$_3$ membrane. Low hysteresis of less than 0.1 V is obtain…
The so-called Boltzmann Tyranny defines the fundamental thermionic limit of the subthreshold slope (SS) of a metal-oxide-semiconductor field-effect transistor (MOSFET) at 60 mV/dec at room temperature and, therefore, precludes the lowering of the supply voltage and the overall power consumption. Adding a ferroelectric negative capacitor to the gate stack of a MOSFET may offer a promising solution to bypassing this fundamental barrier. Meanwhile, two-dimensional (2D) semiconductors, such as atomically thin transition metal dichalcogenides (TMDs) due to their low dielectric constant, and ease of…
This work investigates energy filtering in nanowires, where pass and stopbands are obtained by including superlattices in the wire. When a pair of such superlattices is placed in series, each being controlled by a gate, it can act as a transistor where the (mis-)alignment of its minibands turns the device on (off). It is shown that, in the ballistic current-regime, the transition between the on and off state occurs in a narrow gate-bias range, giving rise to sub-60 mV per decade switching behavior.
Steep transistors are crucial in lowering power consumption of the integrated circuits. However, the difficulties in achieving steepness beyond the Boltzmann limit experimentally have hindered the fundamental challenges in application of these devices in integrated circuits. From a sensitivity perspective, an ideal switch should have a high sensitivity to the gate voltage and lower sensitivity to the device design parameters like oxide and body thicknesses. In this work, conventional tunnel-FET (TFET) and negative capacitance FET are shown to suffer from high sensitivity to device design param…
We propose a Heterojunction Vertical Tunneling FET and show using self-consistent ballistic quantum transport simulations that it can provide very steep subthreshold swings and high ON current, thereby improving the scalability of Tunnel FETs for high performance. The turn-on in pocket region of the device is dictated by modulation of heterojunction barrier height. The steepness of turn-on is increased because of simultaneous onset of tunneling in the pocket and the region underneath and also due to contribution to current by vertical tunneling in the pocket. These factors can be engineered by…
In this work, we investigate the intrinsic limits of subthreshold slope in a dual gated bilayer graphene transistor using a coupled self-consistent Poisson-bandstructure solver. We benchmark the solver by matching the bias dependent bandgap results obtained from the solver against published experimental data. We show that the intrinsic bias dependence of the electronic structure and the self-consistent electrostatics limit the subthreshold slope obtained in such a transistor well above the Boltzmann limit of 60mV/decade at room temperature, but much below the results experimentally shown till …
Ballistic quantum transport calculations based on the non-equilbrium Green's function formalism show that field-effect transistor devices made from chevron-type graphene nanoribbons (CGNRs) could exhibit negative differential resistance with peak-to-valley ratios in excess of 4800 at room temperature as well as steep-slope switching with 6 mV/decade subtheshold swing over five orders of magnitude and ON-currents of 88$μ$A/$μ$m. This is enabled by the superlattice-like structure of these ribbons that have large periodic unit cells with regions of different effective bandgap, resulting in miniba…
The device concept of ferroelectric-based negative capacitance (NC) transistors offers a promising route for achieving energy-efficient logic applications that can outperform the conventional semiconductor technology, while viable operation mechanisms remain a central topic of debate. In this work, we report steep slope switching in MoS$_2$ transistors back-gated by single-layer polycrystalline PbZr$_{0.35}$Ti$_{0.65}$O$_3$. The devices exhibit current on/off ratios up to 8$\times$10$^6$ within an ultra-low gate voltage window of $V_g$ = $\pm$0.5 V and subthreshold swing (SS) as low as 9.7 mV …
The availability of transistors capable of operating at low supply voltage is essential to improve the key performance metric of computing circuits, i.e., the number of operations per unit energy. In this paper, we propose a new device concept for energy-efficient, steep-slope transistors based on heterojunctions of 2D materials. We show that by injecting electrons from an isolated and weakly dispersive band into a strongly dispersive one, subthermionic subthreshold swings can be obtained, as a result of a cold-source effect and of a reduced thermalization of carriers. This mechanism is implem…
Negative capacitance field-effect transistors (NC-FETs) have attracted wide interest as promising candidates for steep-slope devices, and sub-60 mV/decade switching has been demonstrated in NC-FETs with various device structures and material systems. However, the detailed mechanisms of the observed steep-slope switching in some of these experiments are under intense debate. Here we show that sub-60 mV/decade switching can be observed in a WS2 transistor with a metal-insulator-metal-insulator-semiconductor (MIMIS) structure - without any ferroelectric component. This structure resembles an NC-F…
We propose a steep-slope MoS2-nanoribbon field-effect transistor that exploits a narrow-energy conduction band to intrinsically filter out the thermionic tail of the electron energy distribution. We study the device operation principle and the performance dependence on the design parameters through atomistic self-consistent quantum simulations. Our results indicate that the device can provide high ION/IOFF ratios, compatible with electronic applications, albeit biased at ultralow voltages of around 0.1 V.
We report a strategy to design nanoscale cold-source field-effect transistors (CS-FETs) with bias-independent sub-60 mV/dec subthreshold swing (SS). By first-principles calculations and quantum-transport simulations, we reveal that the energy alignment of density of states (DOS) between the drain and source electrodes is critical to achieving bias-independent SS. By defining "gate window", we propose a device model to demonstrate how similar slopes of the drain DOS falling into the gate window can stabilize the SS under different bias. This study underscores the significance of drain DOS engin…
We report on measurements and modeling of FE HfZrO/SiO2 Ferroelectric-Dielectric (FE-DE) FETs which indicate that many of the phenomena attributed to Negative Capacitance can be explained by a delayed response of ferroelectric domain switching - referred to as Transient Negative Capacitance (TNC). No traversal of the stabilized negative capacitance branch is required. Modeling is used to correlate the hysteretic properties of the ferroelectric material to the measured transient and subthreshold slope (SS) behavior. It is found that steep SS can be understood as a transient phenomenon, present …
A vertical transistor based on a double gated, atomically thin heterojunction is theoretically examined. Both p-type and n-type transistor operations can be conveniently achieved by using one of the two gates as the switching gate. The transistor shows excellent saturation of output I-V characteristics due to drain-induced depletion and lack of tunneling barrier layers. The subthreshold slope could be below the thermionic limit due to band filtering as the switching mechanism. The atomically thin vertical PN heterojunction can be electrostatically modulated from a type II heterojunction to a b…
The single particle tunneling in a vertical stack consisting of monolayers of two-dimensional semiconductors is studied theoretically and its application to a novel Two-dimensional Heterojunction Interlayer Tunneling Field Effect Transistor (Thin-TFET) is proposed and described. The tunneling current is calculated by using a formalism based on the Bardeen's transfer Hamiltonian, and including a semi-classical treatment of scattering and energy broadening effects. The misalignment between the two 2D materials is also studied and found to influence the magnitude of the tunneling current, but hav…
We study the transport properties of deeply scaled monolayer MoS2 n-channel metal-oxide-semiconductor field effect transistors (MOSFETs) using full-band ballistic quantum transport simulations with an atomistic tight-binding Hamiltonian obtained from density functional theory. Our simulations suggest that monolayer MoS2 MOSFETs can provide near-ideal subthreshold slope, and suppression of drain-induced barrier lowering (DIBL) and gate-induced drain leakage (GIDL). However, these full-band simulations also exhibit limited transconductance. These ballistic simulations also exhibit negative diffe…
In this work, we simulate the expected device performance and the scaling perspectives of Carbon nanotube Field Effect Transistors (CNT-FETs), with doped source and drain extensions. The simulations are based on the self-consistent solution of the 3D Poisson-Schroedinger equation with open boundary conditions, within the Non-Equilibrium Green's Function formalism, where arbitrary gate geometry and device architecture can be considered. The investigation of short channel effects for different gate configurations and geometry parameters shows that double gate devices offer quasi ideal subthresho…
We study plasma effects in a micromachined high-electron mobility transistor (HEMT) with the microcantilever serving as the gate using the developed a model. The model accounts for mechanical motion of the microcantilever and spatio-temporal variations (plasma effects) of the two-dimensional electron gas(2DEG) system in the transistor channel. The microcantilever mechanical motion is described in the point-mass approximation. The hydrodynamic electron transport model is used to describe distributed electron plasma phenomena in the 2DEG system. Using the developed model, we calculated the respo…
In this work, device performances of tunneling field effect transistors (TFETs) based on phosphorene are explored via self-consistent atomistic quantum transport simulations. Phosphorene is an ultra-thin two-dimensional (2-D) material with a direct band gap suitable for TFETs applications. Our simulation shows that phosphorene TFETs exhibit subthreshold slope (SS) below 60 mV/dec and a wide range of on-current depending on the transport direction due to highly anisotropic band structures of phosphorene. By benchmarking with monolayer MoTe2 TFETs, we predict that phosphorene TFETs oriented in t…
We report a new method to study two level fluctuators (TLFs) by measuring the offset charge induced after applying a sudden step voltage to the gate electrode of a single electron transistor. The offset charge is measured for more than 20 hours for samples made on three different substrates. We find that the offset charge drift follows a logarithmic increase over four orders of magnitude in time and that the logarithmic slope increases linearly with the step voltage. The charge drift is independent of temperature, ruling out thermally activated TLFs and demonstrating that the charge fluctuatio…
We study the effect of polymer coating, pressure and temperature on the electrical characteristics of monolayer WSe2 back-gated transistors with quasi-ohmic Ni/Au contacts. We find that the removal of a layer of poly(methyl methacrylate) or decreasing the pressure change the device conductivity from p to n-type. We study the current-voltage characteristics as a function of the temperature and measure a gate-tunable Schottky barrier at the contacts with a height of 60 meV in flat-band condition. We report and discuss a change in the mobility and the subthreshold slope observed with increasing t…
In this paper we have developed a two dimensional (2D) analytical model for surface potential and drain current for a long channel Dual Material Gate (DMG) Silicon-on-Insulator (SOI) Tunneling Field Effect Transistor (TFET). This model includes the effect of drain voltage, gate metal work function, oxide thickness and silicon film thickness, without assuming a fully depleted channel. The proposed model also includes the effect of charge accumulation at the interface of the two gates and the variation in the tunneling volume with the applied gate voltage. The accuracy of the model is tested usi…
Controlling the insulator-to-2D-metal transition is a promising key to overcome the scaling problem that silicon-based electronic devices will face in the near future. In this context, we examine the channel formation of SrTiO3-based solid-gated field-effect devices in which a 2D metal phase coexists with a semiconductor phase. A non-monotonic voltage-gain transfer characteristic with negative and positive slope regions is observed. We introduce a numerical model that helps to rationalize the experimental findings in terms of the established physics of field-effect transistors and percolation.…
We investigate the design of steep-slope metal-oxide-semiconductor field-effect transistors (MOSFETs) exploiting monolayers of transition metal dihalides as channel materials. With respect to other previously proposed steep-slope transistors, these devices require simplified manufacturing processes, as no confinement of the 2D material is needed, nor any tunneling heterojunction or ferroelectric gate insulators, and only n- or p-type contacts are demanded. We demonstrate their operation by studying an implementation based on monolayer CrI$_2$ through quantum transport simulations. We show that…
An increase in power consumption necessitates a low-power circuit technology to extend Moore's law. Low-power transistors, such as tunnel field-effect transistors (TFETs), negative-capacitance field-effect transistors (NC-FETs), and Dirac-source field-effect transistors (DS-FETs), have been realised to break the thermionic limit of the subthreshold swing (SS). However, a low-power diode rectifier, which breaks the thermionic limit of an ideality factor (n) of 1 at room temperature, has not been proposed yet. In this study, we have realised a DS Schottky diode, which exhibits a steep-slope char…
Weak antilocalization (WAL) and linear magnetoresistance (LMR) are two most commonly observed magnetoresistance (MR) phenomena in topological insulators (TIs) and often attributed to the Dirac topological surface states (TSS). However, ambiguities exist because these phenomena could also come from bulk states (often carrying significant conduction in many TIs) and are observable even in non-TI materials. Here, we demonstrate back-gated ambipolar TI field-effect transistors in (Bi0.04Sb0.96)2Te3 thin films grown by molecular beam epitaxy on SrTiO3(111), exhibiting a large carrier density tunabi…
