Harideep Nair, Prabhu Vellaisamy, Santha Bhasuthkar, John Paul Shen
A set of highly-optimized custom macro extensions is developed for a 7nm CMOS cell library for implementing Temporal Neural Networks (TNNs) that can mimic brain-like sensory processing with extreme energy efficiency. A TNN prototype (13,750 neurons and 315,000 synapses) for MNIST requires only 1.56mm2 die area and consumes only 1.69mW.
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Temporal Neural Networks (TNNs), inspired from the mammalian neocortex, exhibit energy-efficient online sensory processing capabilities. Recent works have proposed a microarchitecture framework for implementing TNNs and demonstrated competitive performance on vision and time-series applications. Building on these previous works, this work proposes TNN7, a suite of nine highly optimized custom macros developed using a predictive 7nm Process Design Kit (PDK), to enhance the efficiency, modularity and flexibility of the TNN design framework. TNN prototypes for two applications are used for evalua…
Temporal Neural Networks (TNNs) use time as a resource to represent and process information, mimicking the behavior of the mammalian neocortex. This work focuses on implementing TNNs using off-the-shelf digital CMOS technology. A microarchitecture framework is introduced with a hierarchy of building blocks including: multi-neuron columns, multi-column layers, and multi-layer TNNs. We present the direct CMOS gate-level implementation of the multi-neuron column model as the key building block for TNNs. Post-synthesis results are obtained using Synopsys tools and the 45 nm CMOS standard cell libr…
Temporal Neural Networks (TNNs) are spiking neural networks that exhibit brain-like sensory processing with high energy efficiency. This work presents the ongoing research towards developing a custom design framework for designing efficient application-specific TNN-based Neuromorphic Sensory Processing Units (NSPUs). This paper examines previous works on NSPU designs for UCR time-series clustering and MNIST image classification applications. Current ideas for a custom design framework and tools that enable efficient software-to-hardware design flow for rapid design space exploration of applica…
TEXEL: A neuromorphic processor with on-chip learning for beyond-CMOS device integration
本文提出混合信号神经形态架构TEXEL，通过片上学习电路集成新型两端和三端器件，弥合CMOS神经形态计算与新兴器件研究之间的差距，并通过芯片测量与仿真验证其器件集成就绪性。
NeRTCAM: CAM-Based CMOS Implementation of Reference Frames for Neuromorphic Processors
本研究首次提出基于CAM的NeRTCAM架构，通过7nm CMOS直接实现神经形态处理器所需的参考帧核心操作，经MNIST推理验证其面积、功耗和延迟均具可行性。
This paper presents an in-memory computing (IMC) architecture for image denoising. The proposed SRAM based in-memory processing framework works in tandem with approximate computing on a binary image generated from neuromorphic vision sensors. Implemented in TSMC 65nm process, the proposed architecture enables approximately 2000X energy savings (approximately 222X from IMC) compared to a digital implementation when tested with the video recordings from a DAVIS sensor and achieves a peak throughput of 1.25-1.66 frames/us.
Temperature-Resilient Analog Neuromorphic Chip in Single-Polysilicon CMOS Technology
本文提出一种温度补偿机制，在单多晶硅CMOS工艺上实现温度鲁棒的模拟神经形态芯片，用于图像识别，在10-60°C范围内保持分类精度，与软件神经网络误差在2%以内。
In this work, we present a hybrid memory bit cell - collocated SRAM and DRAM (CRAM) consisting of 11 transistors for in-memory computing (IMC) based image restoration (IR) and region proposal (RP). A robust RP updated algorithm is proposed to improve the performance. This work demonstrates IMC based global parallel diffusion and column/row-wise projection to achieve a maximal energy efficiency of 1220 TOPS/W for image restoration and 915 TOPS/W when combined with region proposal.
The memristance of a memristor depends on the amount of charge flowing through it and when current stops flowing through it, it remembers the state. Thus, memristors are extremely suited for implementation of memory units. Memristors find great application in neuromorphic circuits as it is possible to couple memory and processing, compared to traditional Von-Neumann digital architectures where memory and processing are separate. Neural networks have a layered structure where information passes from one layer to another and each of these layers have the possibility of a high degree of paralleli…
2T1R Regulated Memristor Conductance Control Array Architecture for Neuromorphic Computing using 28nm CMOS Technology
针对1T1R忆阻器阵列的导线电阻引发的读写干扰等问题，提出28nm工艺下的2T1R调控型电导控制架构，通过双端接地阻漏、调控电流/电压控电导，优化神经形态计算的存内计算能效。
Neuromorphic computing using biologically inspired Spiking Neural Networks (SNNs) is a promising solution to meet Energy-Throughput (ET) efficiency needed for edge computing devices. Neuromorphic hardware architectures that emulate SNNs in analog/mixed-signal domains have been proposed to achieve order-of-magnitude higher energy efficiency than all-digital architectures, however at the expense of limited scalability, susceptibility to noise, complex verification, and poor flexibility. On the other hand, state-of-the-art digital neuromorphic architectures focus either on achieving high energy e…
Neuromorphic vision processor is an electronic implementation of vision algorithm processor on semiconductor. To image the world, a low-power CMOS image sensor array is required in the vision processor. The image sensor array is typically formed through photo diodes and analog to digital converter (ADC). To achieve low power acquisition, a low-power mid-resolution ADC is necessary. In this paper, a 1.8V, 8-bit, 166MS/s pipelined ADC was proposed in a 0.18 um CMOS technology. The ADC used operational amplifier sharing architecture to reduce power consumption and achieved maximum DNL of 0.24 LSB…
The advent of dedicated Deep Learning (DL) accelerators and neuromorphic processors has brought on new opportunities for applying both Deep and Spiking Neural Network (SNN) algorithms to healthcare and biomedical applications at the edge. This can facilitate the advancement of medical Internet of Things (IoT) systems and Point of Care (PoC) devices. In this paper, we provide a tutorial describing how various technologies including emerging memristive devices, Field Programmable Gate Arrays (FPGAs), and Complementary Metal Oxide Semiconductor (CMOS) can be used to develop efficient DL accelerat…
NeuDW-CIM: a 65-nm 0.8-pJ/Sop Reconfigurable Neuromorphic Compute-in-Memory Macro with Nonlinear Dendrites and K-Winners
本文提出NeuDW-CIM，一种65纳米CMOS的高效神经形态存内计算宏单元，通过可重构非线性内存模数转换器实现非线性树突和K胜者模式，在N-MNIST和DVS Gesture数据集上分别达到97.2%和95.5%的准确率，能效为0.8皮焦/突触操作。
Design and Development of a Neuromorphic Silicon Suite: PVT Sensing, Stochastic LIF Inference, On-Chip STDP Learning, and Crossbar Programming
本文设计了一套兼容接口的数字IP模块，包括PVT传感器、随机LIF神经元、片上STDP控制器和忆阻交叉阵列控制器，在SkyWater 130 nm工艺上实现，通过SPI统一接口，经Tiny Tapeout提交流片。
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