利用粗粒度单片3D（M3D）集成减轻DRAM设计的延迟-面积权衡
Mitigating the Latency-Area Tradeoffs for DRAM Design with Coarse-Grained Monolithic 3D (M3D) Integration
摘要：
多年来，由于DRAM行业以成本为中心的心态，DRAM延迟并未与其密度成比例地扩展。先前的工作表明，这个缺点可以通过减少DRAM访问路径的临界长度来克服。然而，这样做降低了DRAM面积效率，加剧了DRAM设计的延迟面积权衡。在本文中，我们表明，重组DRAM单元阵列使用新兴的单片3D（M3 D）集成技术可以减轻这些基本的延迟面积权衡。根据PARSEC基准测试的评估结果，与传统的2D DDR4 DRAM相比，我们设计的M3 D DRAM单元阵列组织可以减少高达9.56%的延迟，减少高达4.96%的功耗，减少高达21.21%的能量延迟积（EDP），减少高达14%的DRAM芯片面积。
英文摘要：
Over the years, the DRAM latency has not scaled proportionally with its density due to the cost-centric mindset of the DRAM industry. Prior work has shown that this shortcoming can be overcome by reducing the critical length of DRAM access path. However, doing so decreases DRAM area-efficiency, exacerbating the latency-area tradeoffs for DRAM design. In this paper, we show that reorganizing DRAM cell-arrays using the emerging monolithic 3D (M3D) integration technology can mitigate these fundamental latency-area tradeoffs. Based on our evaluation results for PARSEC benchmarks, our designed M3D DRAM cell-array organizations can yield up to 9.56% less latency, up to 4.96% less power consumption, and up to 21.21% less energy-delay product (EDP), with up to 14% less DRAM die area, com-pared to the conventional 2D DDR4 DRAM.
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