考虑数据共享和一致性的多核共享Cache行为分析建模
Analytical Modeling the Multi-Core Shared Cache Behavior with Considerations of Data-Sharing and Coherence
摘要：
为了缓解日益恶化的“功率墙”和“存储墙”问题，具有多级缓存层次的多核体系结构已被广泛接受在现代处理器中。然而，架构的复杂性使得共享缓存的建模极其复杂。在本文中，我们提出了一个数据共享感知的分析模型，估计多核场景下的下游共享缓存的未命中率。此外，该模型还可以与上游缓存分析模型集成，考虑多核私有缓存的一致性效应。这种集成避免了传统方法所需的高速缓存架构的耗时的完全模拟。我们验证了我们的分析模型对gem5的模拟结果下13个应用程序PARSEC 2.1基准套件。与包括双核和四核架构在内的8种硬件配置下的gem5仿真结果相比，所有配置下共享二级缓存未命中率的预测平均绝对误差均小于2%。与改进的上游模型相结合后，由于误差累积，4种硬件配置的总体平均绝对误差降低到8.03%。所提出的一致性模型可以实现类似的精度的最先进的方法，只有十分之一的时间开销。作为综合模型的应用案例，我们还评估了57个不同的多核和多级缓存配置的未命中率。
英文摘要：
To mitigate the ever worsening "Power wall" and "Memory wall" problems, multi-core architectures with multilevel cache hierarchies have been widely accepted in modern processors. However, the complexity of the architectures makes modeling of shared caches extremely complex. In this paper, we propose a data-sharing aware analytical model for estimating the miss rates of the downstream shared cache under multi-core scenarios. Moreover, the proposed model can also be integrated with upstream cache analytical models with the consideration of multi-core private cache coherent effects. This integration avoids time consuming full simulations of the cache architecture that required by conventional approaches. We validate our analytical model against gem5 simulation results under 13 applications from PARSEC 2.1 benchmark suites. Compared to the results from gem5 simulations under 8 hardware configurations including dual-core and quad-core architectures, the average absolute error of the predicted shared L2 cache miss rates is less than 2% for all configurations. After integrated with the refined upstream model with coherence misses, the overall average absolute error in 4 hardware configurations is degraded to 8.03% due to the error accumulations. The proposed coherence model can achieve similar accuracies of state of the art approach with only one tenth time overhead. As an application case of the integrated model, we also evaluate the miss rates of 57 different multi-core and multi-level cache configurations.
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