Spin qubits in quantum dots define an attractive platform for scalable quantum information because of their compatibility with semiconductor manufacturing, their long coherence times, and the ability to operate at temperatures exceeding one Kelvin. Qubit logic can be implemented by pulsing the exchange interaction or via driven rotations. Here, we show that these approaches can be combined to execute a multitude of native two-qubit gates in a single device, reducing the operation overhead to perform quantum algorithms. We demonstrate, at a temperature above one Kelvin, single-qubit rotations together with the two-qubit gates CROT, CPHASE and SWAP. Furthermore we realize adiabatic, diabatic and composite sequences to optimize the qubit control fidelity and the gate time. We find two-qubit gates that can be executed within 67 ns and by theoretically analyzing the experimental noise sources we predict fidelities exceeding 99%. This promises fault-tolerant operation using quantum hardware that can be embedded with classical electronics for quantum integrated circuits.
Recent studies of silicon spin qubits at temperatures above 1 K are encouraging demonstrations that the cooling requirements for solid-state quantum computing can be considerably relaxed. However, qubit readout mechanisms that rely on charge sensing with a single-island single-electron transistor (SISET) quickly lose sensitivity due to thermal broadening of the electron distribution in the reservoirs. Here we exploit the tunneling between two quantised states in a double-island SET (DISET) to demonstrate a charge sensor with an improvement in signal-to-noise by an order of magnitude compared t…
We report electronic transport on silicon double and triple dots created with the optimized number of two gates. Using silicon nitride spacers two dots in series are created below two top gates overlapping a silicon nanowire. Coupling between dots is controlled by gate voltages. A third dot is created either by combined action of gate voltages or local doping depending on the spacers length. The main characteristics of the triple dot stability diagram are quantitatively fitted.
In this letter we discuss how the short channel behavior in sub 100 nm channel range can be improved by inducing a step surface potential profile at the back gate of an asymmetrical double gate (DG) Silicon-On-Insulator (SOI) Metal-Oxide-Semiconductor Field-Effect- Transistor (MOSFET) in which the front gate consists of two materials with different work functions.
Silicon-based quantum computing has the potential advantages of low cost, high integration density, and compatibility with CMOS technologies. The detuning mechanism has been used to experimentally achieve silicon two-qubit quantum gates and programmable quantum processors. In this paper, the scaling behaviors and variability issues are explored by numerical device simulations of a model silicon quantum gate based on the detuning mechanism. The device physics of quantum gates modulation, tradeoff between device speed and quantum fidelity, and impact of variability on the implementation of a qua…
We report electron transport measurements of a silicon double dot formed in multi-gated metal-oxide-semiconductor structures with a 15-nm-thick silicon-on-insulator layer. Tunable tunnel coupling enables us to observe an excitation spectrum in weakly coupled dots and an energy level anticrossing in strongly coupled ones. Such a quantum dot molecule with both charge and energy quantization provides the essential prerequisite for future implementation of silicon-based quantum computations.
Two-qubit quantum gates play an essential role in quantum computing, whose operation critically depends on the entanglement between two qubits. Resonantly driven controlled-NOT (CNOT) gates based on silicon double quantum dots (DQDs) are studied theoretically. The physical mechanisms for effective gate modulation of the exchange coupling between two qubits are elucidated. Scaling behaviors of the singlet-triplet energy split, gate-switching speed, and gate fidelity are investigated as a function of the quantum dot spacing and modulation gate voltage. It is shown that the entanglement strength …
We demonstrate the proof of principle for a ternary adder using silicon metal-on-insulator single electron transistors (SET). Gate dependent rectifying behavior of a single electron transistor results in a robust three-valued output as a function of the potential of the SET island. Mapping logical, ternary inputs to the three gates controlling the potential of the SET island allows us to perform complex, inherently ternary operations, on a single transistor.
Quantum computers are expected to outperform conventional computers for a range of important problems, from molecular simulation to search algorithms, once they can be scaled up to large numbers of quantum bits (qubits), typically millions. For most solid-state qubit technologies, e.g. those using superconducting circuits or semiconductor spins, scaling poses a significant challenge as every additional qubit increases the heat generated, while the cooling power of dilution refrigerators is severely limited at their operating temperature below 100 mK. Here we demonstrate operation of a scalable…
We investigate by low-temperature transport experiments the sub-threshold behavior of triple-gate silicon field-effect transistors. These three-dimensional nano-scale devices consist of a lithographically defined silicon nanowire surrounded by a gate with an active region as small as a few tens of nanometers, down to 50x60x35 nm^3. Conductance versus gate voltage show Coulomb-blockade oscillations with a large charging energy due to the formation of a small potential well below the gate. According to dependencies on device geometry and thermionic current analysis, we conclude that sub-threshol…
The low temperature properties of glass are distinct from those of crystals due to the presence of poorly understood low-energy excitations. The tunneling model proposes that these are atoms tunneling between nearby equilibria, forming tunneling two level systems (TLSs). This model is rather successful, but it does not explain the remarkably universal value of the mechanical dissipation $Q^{-1}$ near 1 kelvin. The only known exceptions to this universality are the $Q^{-1}$ of certain thin films of amorphous silicon, carbon and germanium. Recently, it was found that $Q^{-1}$ of amorphous silico…
We replace the established aluminium gates for the formation of quantum dots in silicon with gates made from palladium. We study the morphology of both aluminium and palladium gates with transmission electron microscopy. The native aluminium oxide is found to be formed all around the aluminium gates, which could lead to the formation of unintentional dots. Therefore, we report on a novel fabrication route that replaces aluminium and its native oxide by palladium with atomic-layer-deposition-grown aluminium oxide. Using this approach, we show the formation of low-disorder gate-defined quantum d…
We report on the electronic transport properties of multiple-gate devices fabricated from undoped silicon nanowires. Understanding and control of the relevant transport mechanisms was achieved by means of local electrostatic gating and temperature dependent measurements. The roles of the source/drain contacts and of the silicon channel could be independently evaluated and tuned. Wrap gates surrounding the silicide-silicon contact interfaces were proved to be effective in inducing a full suppression of the contact Schottky barriers, thereby enabling carrier injection down to liquid-helium tempe…
We show that silicon nitride can provide uniform coverage of graphene in field-effect transistors while preserving the channel mobility. This insulator allowed us to study the maximum channel resistance at the Dirac (neutrality) point as a function of the strength of a perpendicular electric field in top-gated devices with different numbers of graphene layers. Using a simple model to account for surface potential variations (electron-hole puddles) near the Dirac point we estimate the field-induced band-gap or band-overlap in the different layers.
Sensitive charge detection has enabled qubit readout in solid-state systems. Recently, an alternative to the well-established charge detection via on-chip electrometers has emerged, based on in situ gate detectors and radio-frequency dispersive readout techniques. This approach promises to facilitate scalability by removing the need for additional device components devoted to sensing. Here, we perform gate-based dispersive readout of an accumulation-mode silicon quantum dot. We observe that the response of an accumulation-mode gate detector is significantly affected by its bias voltage, partic…
We implement silicon quantum dot devices with two layers of gate electrodes using a self-alignment technique, which allows for ultra-small gate lengths and intrinsically perfect layer-to-layer alignment. In a double quantum dot system, we investigate hole transport and observe current rectification due to Pauli spin blockade. Magnetic field measurements indicate that hole spin relaxation is dominated by spin-orbit interaction, and enable us to determine the effective hole $g$-factor $\simeq1.6$. From an avoided singlet-triplet crossing, occurring at high magnetic field, the spin-orbit coupling…
Silicon spin qubits have emerged as a promising path to large-scale quantum processors. In this prospect, the development of scalable qubit readout schemes involving a minimal device overhead is a compelling step. Here we report the implementation of gate-coupled rf reflectometry for the dispersive readout of a fully functional spin qubit device. We use a p-type double-gate transistor made using industry-standard silicon technology. The first gate confines a hole quantum dot encoding the spin qubit, the second one a helper dot enabling readout. The qubit state is measured through the phase res…
Novel spin transport behavior is theoretically shown to result from replacing the usual metal (or poly-silicon) gate in a silicon field-effect transistor with a ferromagnet, separated from the semiconductor by an ultra-thin oxide. The spin-dependent interplay between the drift current (due to a source-drain bias) and the diffusion current (due to carrier leakage into the ferromagnetic gate) results in a rich variety of spin dependence in the current that flows through such a device. We examine two cases of particular interest: (1) creating a 100% spin-polarized electrical current and (2) creat…
We present a gate-voltage tunable transmon qubit (gatemon) based on planar InAs nanowires that are selectively grown on a high resistivity silicon substrate using III-V buffer layers. We show that low loss superconducting resonators with an internal quality of $2\times 10^5$ can readily be realized using these substrates after the removal of buffer layers. We demonstrate coherent control and readout of a gatemon device with a relaxation time, $T_{1}\approx 700\,\mathrm{ns}$, and dephasing times, $T_2^{\ast}\approx 20\,\mathrm{ns}$ and $T_{\mathrm{2,echo}} \approx 1.3\,\mathrm{μs}$. Further, we…
We present a novel reconfigurable metal-oxide-semiconductor multi-gate transistor that can host a quadruple quantum dot in silicon. The device consist of an industrial quadruple-gate silicon nanowire field-effect transistor. Exploiting the corner effect, we study the versatility of the structure in the single quantum dot and the serial double quantum dot regimes and extract the relevant capacitance parameters. We address the fabrication variability of the quadruple-gate approach which, paired with improved silicon fabrication techniques, makes the corner state quantum dot approach a promising …
A requirement for quantum information processors is the in-situ tunability of the tunnel rates and the exchange interaction energy within the device. The large energy level separation for atom qubits in silicon is well suited for qubit operation but limits device tunability using in-plane gate architectures, requiring vertically separated top-gates to control tunnelling within the device. In this paper we address control of the simplest tunnelling device in Si:P, the tunnel junction. Here we demonstrate that we can tune its conductance by using a vertically separated top-gate aligned with +-5n…
The presence of degenerate conduction band valleys and how they are mixed by interfaces play critical roles in determining electron interaction and spectrum in a silicon nanostructure. Here we investigate how the valley phases affect the exchange interaction in a symmetric two-electron silicon double quantum dot. Through a configuration interaction calculation, we find that exchange splitting is suppressed at a finite value of valley phase difference between the two dots, and reaches its minimum value ({\sim} 0) when the phase difference is π. Such a suppression can be explained using the Hubb…
We investigate the electrical control of the exchange coupling (J) between donor bound electrons in silicon with a detuning gate bias, crucial for the implementation of the two-qubit gate in a silicon quantum computer. We find the asymmetric 2P-1P system provides a highly tunable exchange-curve with mitigated J-oscillation, in which 5 orders of magnitude change in the exchange energy can be achieved using a modest range of electric field for 15 nm qubit separation. Compared to the barrier gate control of exchange in the Kane qubit, the detuning gate design reduces the demanding constraints of …
Many electrical applications of quantum dots rely on capacitively coupled gates; therefore, to make reliable devices we need those gate capacitances to be predictable and reproducible. We demonstrate in silicon nanowire quantum dots that gate capacitances are reproducible to within 10% for nominally identical devices. We demonstrate the experimentally that gate capacitances scale with device dimensions. We also demonstrate that a capacitance simulator can be used to predict measured gate capacitances to within 20%. A simple parallel plate capacitor model can be used to predict how the capacita…
An evaluation of the gate capacitance of a field-effect transitor (FET) whose channel length and width are several ten nanometer, is a key point for sensors applications. However, experimental and precise evaluation of capacitance in the aF range or less has been extremely difficult. Here, we report an extraction of the capacitance down to 0.55 aF for a silicon FET with a nanoscale wire channel whose width and length are 15 and 50 nm, respectively. The extraction can be achieved by using a combination of four kinds of measurements: current characteristics modulated by double gates, random-tele…
We report on dual-gate reflectometry in a metal-oxide-semiconductor double-gate silicon transistor operating at low temperature as a double quantum dot device. The reflectometry setup consists of two radio-frequency resonators respectively connected to the two gate electrodes. By simultaneously measuring their dispersive response, we obtain the complete charge stability diagram of the device. Charge transitions between the two quantum dots and between each quantum dot and either the source or the drain contact are detected through phase shifts in the reflected radio-frequency signals. At finit…
We present transport measurements of a tunable silicon metal-oxide-semiconductor double quantum dot device with lateral geometry. Experimentally extracted gate-to-dot capacitances show that the device is largely symmetric under the gate voltages applied. Intriguingly, these gate voltages themselves are not symmetric. Comparison with numerical simulations indicates that the applied gate voltages serve to offset an intrinsic asymmetry in the physical device. We also show a transition from a large single dot to two well isolated coupled dots, where the central gate of the device is used to contro…
The greatest challenge in quantum computing is achieving scalability. Classical computing previously faced a scalability issue, solved with silicon chips hosting billions of fin field-effect transistors (FinFETs). These FinFET devices are small enough for quantum applications: at low temperatures, an electron or hole trapped under the gate serves as a spin qubit. Such an approach potentially allows the quantum hardware and its classical control electronics to be integrated on the same chip. However, this requires qubit operation at temperatures above 1K, where the cooling overcomes heat dissip…
Graphene/silicon (G/Si) heterojunction based devices have been demonstrated as high responsivity photodetectors that are potentially compatible with semiconductor technology. Such G/Si Schottky junction diodes are typically in parallel with gated G/silicon dioxide (SiO$_2$)/Si areas, where the graphene is contacted. Here, we utilize scanning photocurrent measurements to investigate the spatial distribution and explain the physical origin of photocurrent generation in these devices. We observe distinctly higher photocurrents underneath the isolating region of graphene on SiO$_2$ adjacent to the…
We present a systematic study of various ways (top gates, local doping, substrate bias) to fabricate and tune multi-dot structures in silicon nanowire multigate MOSFETs (metal-oxide-semiconductor field-effect transistors). The carrier concentration profile of the silicon nanowire is a key parameter to control the formation of tunnel barriers and single-electron islands. It is determined both by the doping profile of the nanowire and by the voltages applied to the top gates and to the substrate. Local doping is achieved with the realisation of up to two arsenic implantation steps in combination…
The three-qubit Toffoli gate plays an important role in quantum error correction and complex quantum algorithms such as Shor's factoring algorithm, motivating the search for efficient implementations of this gate. Here we introduce a Toffoli gate suitable for exchange-coupled electron spin qubits in silicon quantum dot arrays. Our protocol is a natural extension of a previously demonstrated resonantly driven CNOT gate for silicon spin qubits. It is based on a single exchange pulse combined with a resonant microwave drive, with an operation time on the order of 100 ns and fidelity exceeding 99%…
An error-corrected quantum processor will require millions of qubits, accentuating the advantage of nanoscale devices with small footprints, such as silicon quantum dots. However, as for every device with nanoscale dimensions, disorder at the atomic level is detrimental to qubit uniformity. Here we investigate two spin qubits confined in a silicon double-quantum-dot artificial molecule. Each quantum dot has a robust shell structure and, when operated at an occupancy of 5 or 13 electrons, has single spin-$\frac{1}{2}$ valence electron in its $p$- or $d$-orbital, respectively. These higher elect…
We report on ambipolar gate-defined quantum dots in silicon on insulator (SOI) nanowires fabricated using a customised complementary metal-oxide-semiconductor (CMOS) process. The ambipolarity was achieved by extending a gate over an intrinsic silicon channel to both highly doped n-type and p-type terminals. We utilise the ability to supply ambipolar carrier reservoirs to the silicon channel to demonstrate an ability to reconfigurably define, with the same electrodes, double quantum dots with either holes or electrons. We use gate-based reflectometry to sense the inter-dot charge transition(IDT…
We have performed numerical modeling of dual-gate ballistic n-MOSFET's with channel length of the order of 10 nm, including the effects of quantum tunneling along the channel and through the gate oxide. Our analysis includes a self-consistent solution of the full (two-dimensional) electrostatic problem, with account of electric field penetration into the heavily-doped electrodes. The results show that transistors with channel length as small as 8 nm can exhibit either a transconductance up to 4,000 mS/mm or gate modulation of current by more than 8 orders of magnitude, depending on the gate ox…
Transport measurements at cryogenic temperatures through a few electron top gated quantum dot fabricated in a silicon/silicon-germanium heterostructure are reported. Variations in gate voltage induce a transition from an isolated dot toward a dot strongly coupled to the leads. In addition to Coulomb blockade, when the dot is strongly coupled to the leads, we observe the appearance of a zero bias conductance peak due to the Kondo effect. The Kondo peak splits in a magnetic field, and the splitting scales linearly with the applied field. We also observe a transition from pure Coulomb blockade to…
Previous cryogenic electronics studies are most above 4.2K. In this paper we present the cryogenic characterization of a 0.18μm standard bulk CMOS technology(1.8V and 5V) at sub-kelvin temperature around 270mK. PMOS and NMOS devices with different width to length ratios(W/L) are tested and characterized under various bias conditions at temperatures from 300K to 270mK. It is shown that the 0.18μm standard bulk CMOS technology is still working at sub-kelvin temperature. The kink effect and current overshoot phenomenon are observed at sub-kelvin temperature. Especially, current overshoot phenomen…
Single qubit rotations and two-qubit CNOT operations are crucial ingredients for universal quantum computing. While high fidelity single qubit operations have been achieved using the electron spin degree of freedom, realizing a robust CNOT gate has been a major challenge due to rapid nuclear spin dephasing and charge noise. We demonstrate an efficient resonantly-driven CNOT gate for electron spins in silicon. Our platform achieves single-qubit rotations with fidelities >99%, as verified by randomized benchmarking. Gate control of the exchange coupling allows a quantum CNOT gate to be implement…
Elastic strain changes the energies of the conduction band in a semiconductor, which will affect transport through a semiconductor nanostructure. We show that the typical strains in a semiconductor nanostructure from metal gates are large enough to create strain-induced quantum dots (QDs). We simulate a commonly used QD device architecture, metal gates on bulk silicon, and show the formation of strain-induced QDs. The strain-induced QD can be eliminated by replacing the metal gates with poly-silicon gates. Thus strain can be as important as electrostatics to QD device operation operation.
We report on low-temperature electronic transport measurements of a silicon metal-oxide-semiconductor quantum dot, with independent gate control of electron densities in the leads and the quantum dot island. This architecture allows the dot energy levels to be probed without affecting the electron density in the leads, and vice versa. Appropriate gate biasing enables the dot occupancy to be reduced to the single-electron level, as evidenced by magnetospectroscopy measurements of the ground state of the first two charge transitions. Independent gate control of the electron reservoirs also enabl…
The implementation of a quantum computer requires a qubit-specific measurement capability to read-out the final state of a quantum system. The model of spin dependent tunneling followed by charge readout has been highly successful in enabling spin qubit experiments in all-electrical, semiconductor based quantum computing. As experiments grow more sophisticated, and head towards multiple qubit architectures that enable small scale computation, it becomes important to consider the charge read-out overhead. With this in mind, Reilly et al. demonstrated a gate readout scheme in a GaAs double quant…
We investigate gate-defined quantum dots in silicon on insulator nanowire field-effect transistors fabricated using a foundry-compatible fully-depleted silicon-on-insulator (FD-SOI) process. A series of split gates wrapped over the silicon nanowire naturally produces a $2\times n$ bilinear array of quantum dots along a single nanowire. We begin by studying the capacitive coupling of quantum dots within such a 2$\times$2 array, and then show how such couplings can be extended across two parallel silicon nanowires coupled together by shared, electrically isolated, 'floating' electrodes. With one…
We present transport measurements of silicon MOS split gate structures with and without Sb implants. We observe classical point contact (PC) behavior that is free of any pronounced unintentional resonances at liquid He temperatures. The implanted device has resonances superposed on the point contact transport indicative of transport through the Sb donors. We fit the differential conductance to a rectangular tunnel barrier model with a linear barrier height dependence on source-drain voltage and non-linear dependence on gate bias. Effects such as Fowler-Nordheim (FN) tunneling and image charge …
Solid state quantum processors based on spins in silicon quantum dots are emerging as a powerful platform for quantum information processing. High fidelity single- and two-qubit gates have recently been demonstrated and large extendable qubit arrays are now routinely fabricated. However, two-qubit gates are mediated through nearest-neighbor exchange interactions, which require direct wavefunction overlap. This limits the overall connectivity of these devices and is a major hurdle to realizing error correction, quantum random access memory, and multi-qubit quantum algorithms. To extend the conn…
Isolated spins in semiconductors provide a promising platform to explore quantum mechanical coherence and develop engineered quantum systems. Silicon has attracted great interest as a host material for developing spin qubits because of its weak spin-orbit coupling and hyperfine interaction, and several architectures based on gate defined quantum dots have been proposed and demonstrated experimentally. Recently, a quantum dot hybrid qubit formed by three electrons in double quantum dot was proposed, and non-adiabatic pulsed-gate operation was implemented experimentally, demonstrating simple and…
Addressability of spin qubits in a silicon double quantum dot setup in the (1,1) charge configuration relies on having a large difference between the Zeeman splittings of the electrons. When the difference is not sufficiently large, the rotating wave approximation becomes inaccurate. We consider a device working in this regime, with always-on exchange coupling, and describe how a CZ gate and arbitrary one-qubit gates which are robust against charge noise can be implemented by smoothly pulsing the microwave source, while eliminating the crosstalk. We find that the most significant deviations fr…
This study alleviates the low operating temperature constraint of Si qubits. A qubit is a key element for quantum sensors, memories, and computers. Electron spin in Si is a promising qubit, as it allows both long coherence times and potential compatibility with current silicon technology. Si qubits have been implemented using gate-defined quantum dots or shallow impurities. However, operation of Si qubits has been restricted to milli-Kelvin temperatures, thus limiting the application of the quantum technology. In this study, we addressed a single deep impurity, having strong electron confineme…
Control of entanglement between qubits at distant quantum processors using a two-qubit gate is an essential function of a scalable, modular implementation of quantum computation. Among the many qubit platforms, spin qubits in silicon quantum dots are promising for large-scale integration along with their nanofabrication capability. However, linking distant silicon quantum processors is challenging as two-qubit gates in spin qubits typically utilize short-range exchange coupling, which is only effective between nearest-neighbor quantum dots. Here we demonstrate a two-qubit gate between spin qub…
Silicon can be isotopically enriched, allowing for the fabrication of highly coherent semiconductor spin qubits. However, the conduction band of bulk Si exhibits a six-fold valley degeneracy, which may adversely impact the performance of silicon quantum devices. To date, the spatial characterization of valley states in Si remains limited. Moreover, techniques for probing valley states in functional electronic devices are needed. We describe here a cryogen-free scanning gate microscope for the characterization of Si/Si$_{0.7}$Ge$_{0.3}$ quantum devices at mK temperatures. The microscope is base…
We propose a method to electrically control electron spins in donor-based qubits in silicon. By taking advantage of the hyperfine coupling difference between a single-donor and a two-donor quantum dot, spin rotation can be driven by inducing an electric dipole between them and applying an alternating electric field generated by in-plane gates. These qubits can be coupled with exchange interaction controlled by top detuning gates. The qubit device can be fabricated deep in the silicon lattice with atomic precision by scanning tunneling probe technique. We have combined a large-scale full band a…
A Comprehensive Study of Charge-Carrier Mobility in Double Lateral-Gate Silicon Junctionless Transistors
Laye Rooyan Part, Isfahan Science and Technology Town（拉耶鲁扬部分，伊斯法罕科技城）；Department of Physics, Isfahan University of Technology（伊斯法罕理工大学物理系）；Institute of Microengineering and Nanoelectronics, Universiti Kebangsaan Malaysia（马来西亚国立大学微工程与纳米电子研究所）；Department of Electrical and Computer Engineering, University of Texas at Dallas（德克萨斯大学达拉斯分校电气与计算机工程系）
The dipole trap model is able to explain the main properties of the apparent metal-to-insulator transition in gated high mobility Si-inversion layers. Our numerical calculations are compared with previous analytical ones and the assumptions of the model are discussed carefully. In general we find a similar behavior but include further details in the calculation. The calculated strong density dependence of the resistivity is not yet in full agreement with the experiment.
Building upon the demonstration of coherent control and single-shot readout of the electron and nuclear spins of individual 31-P atoms in silicon, we present here a systematic experimental estimate of quantum gate fidelities using randomized benchmarking of 1-qubit gates in the Clifford group. We apply this analysis to the electron and the ionized 31-P nucleus of a single P donor in isotopically purified 28-Si. We find average gate fidelities of 99.95 % for the electron, and 99.99 % for the nuclear spin. These values are above certain error correction thresholds, and demonstrate the potential …
Universal quantum computation will require qubit technology based on a scalable platform, together with quantum error correction protocols that place strict limits on the maximum infidelities for one- and two-qubit gate operations. While a variety of qubit systems have shown high fidelities at the one-qubit level, superconductor technologies have been the only solid-state qubits manufactured via standard lithographic techniques which have demonstrated two-qubit fidelities near the fault-tolerant threshold. Silicon-based quantum dot qubits are also amenable to large-scale manufacture and can ac…
For solid-state spin qubits, single-gate RF readout can help minimise the number of gates required for scale-up to many qubits since the readout sensor can integrate into the existing gates required to manipulate the qubits (Veldhorst 2017, Pakkiam 2018). However, a key requirement for a scalable quantum computer is that we must be capable of resolving the qubit state within single-shot, that is, a single measurement (DiVincenzo 2000). Here we demonstrate single-gate, single-shot readout of a singlet-triplet spin state in silicon, with an average readout fidelity of $82.9\%$ at a $3.3~\text{kH…
