自适应频率调整的机器学习流水线阶段
A Machine Learning Pipeline Stage for Adaptive Frequency Adjustment
摘要：
提出了一种基于指令传播延迟自适应调整时钟频率的机器学习设计框架。利用当前操作类型、当前操作数和计算历史作为ML特征，训练随机森林模型以实时的对传播延迟进行分类。训练的模型在Verilog中实现为基线处理器内的附加流水线阶段。改进后的系统在45 nm CMOS工艺的门级进行了实验测试，表现出70%的加速比和30%的能量减少与粗粒度ML分类。一个89%的加速比证明了更精细的粒度与15.5%的能耗减少。
英文摘要：
A machine learning (ML) design framework is proposed for adaptively adjusting clock frequency based on propagation delay of individual instructions. A random forest model is trained to classify propagation delays in real time, utilizing current operation type, current operands, and computation history as ML features. The trained model is implemented in Verilog as an additional pipeline stage within a baseline processor. The modified system is experimentally tested at the gate level in 45 nm CMOS technology, exhibiting a speedup of 70% and energy reduction of 30% with coarse-grained ML classification. A speedup of 89% is demonstrated with finer granularities with 15.5% reduction in energy consumption.
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