G. Balbi, M. Barbero, R. Beccherle, M. Bindi, P. Breugnon, P. Butti, D. Cinca, J. Dickinson, D. Ferrere, D. Fougeron, M. Garcia-Sciveres, J. Garcia Pascual, A. … 展开作者
G. Balbi, M. Barbero, R. Beccherle, M. Bindi, P. Breugnon, P. Butti, D. Cinca, J. Dickinson, D. Ferrere, D. Fougeron, M. Garcia-Sciveres, J. Garcia Pascual, A. Gaudiello, C. Gemme, N. Giangiacomi, T. Hemperek, L. Jeanty, O. Kepka, M. Kocian, K. Lantzsch, P. Liu, C. Martin, A. Mekkaoui, M. Menouni, K. Potamianos, A. Rozanov, Y. Takubo, M. Wensing
Effects of Single Event Upsets (SEU) and Single Event Transients (SET) are studied in the FE-I4B chip of the innermost layer of the ATLAS pixel system. SEU/SET affect the FE-I4B Global Registers as well as the settings for the individual pixels, causing, among other things, occupancy losses, drops in the low voltage currents, noisy pixels, and silent pixels. Quantitative data analysis and simulations indicate that SET dominate over SEU on the load line of the memory. Operational issues and mitigation techniques are presented.
The ATLAS Insertable B-Layer (IBL) detector was installed into the ATLAS experiment in 2014 and has been in operation since 2015. During the first year of IBL data taking an increase of the low voltage currents associated with the FE-I4 front-end chip was observed and this increase was traced back to the radiation damage in the chip. The dependence of the current on the total-ionising dose and temperature has been tested with X-ray and proton irradiations and will be presented in this paper together with the detector operation guidelines.
ATLAS探测器将进行升级，以实现LHC的更高强度运行。在所谓的第一阶段运行之前，预计2016年将长期关闭。一个新的像素层，称为可插入B层（IBL），将被插入在现有的像素探测器和一个新的（更小半径）光束管之间的半径约为3.2厘米。IBL需要开发几种新技术来应对增加的辐射水平和像素占用，以及改善现有像素探测器的物理性能。IBL项目为整个ATLAS跟踪器的第二阶段升级提供了一个技术测试，其亮度约为10^35 cm^-2 s ^-1。该项目的概述，特别强调IBL布局和预期的性能，以及模块开发，包括杂交技术。
The ATLAS Insertable B-Layer (IBL) is the innermost layer of pixel detectors, and was installed in May 2014 at a radius of 3.3 cm from the beam axis, between the existing Pixel detector and a new smaller radius beam-pipe. The new detector, built to cope with high radiation and occupancy, is the first large scale application of 3D sensors and CMOS 130 nm technology. The IBL detector construction was completed within about two years (2012-2014), and the key features and challenges met during the IBL project are presented, as well as its commissioning and operational experience at the LHC.
Planar silicon pixel sensors with modified n$^+$-implantation shapes based on the IBL pixel sensor were designed in Dortmund. The sensors with a pixel size of $250\,μ$m $\times$ $50\,μ$m are produced in n$^+$-in-n sensor technology. The charge collection efficiency should improve with electrical field strength maxima created by the different n$^+$-implantation shapes. Therefore, higher particle detection efficiencies at lower bias voltages could be achieved. The modified pixel designs and the IBL standard design are placed on one sensor to test and compare the designs. The sensor can be read o…
Run-2 of the Large Hadron Collider (LHC) will provide new challenges to track and vertex reconstruction with higher energies, denser jets and higher rates. Therefore the ATLAS experiment has constructed the first 4-layer Pixel Detector in HEP, installing a new pixel layer, also called Insertable B-Layer (IBL). The IBL is a fourth layer of pixel detectors, and has been installed in May 2014 at a radius of 3.3 cm between the existing Pixel Detector and a new smaller radius beam-pipe. The new detector, built to cope with the high radiation and expected occupancy, is the first large scale applicat…
Single Event Effects (SEEs) - predominately bit-flips in electronics caused by particle interactions - are a major concern for ASICs operated in high radiation environments such as ABCStar ASICs, which are designed to be used in the future ATLAS ITk strip tracker. The chip design is therefore optimised to protect it from SEEs by implementing triplication techniques such as Triple Modular Redundancy (TMR). In order to verify the radiation protection mechanisms of the chip design, the cross-section for Single Event Upsets (SEUs), a particular class of SEEs, is measured by exposing the chip to hi…
The innermost part of the tracking detector of the ATLAS experiment consists mainly of planar n$^+$-in-n silicon pixel sensors. During the phase-0 upgrade, the Insertable B-Layer (IBL) was installed closest to the beam pipe. Its pixels are arranged with a pitch of $250\,μ$m$\,\times\,50\,μ$m with a rectangular shaped n$^+$ implantation. Based on this design modified pixel designs have been developed in Dortmund. Six of these new pixel designs are arranged in structures of ten columns and were placed beside structures with the standard design on one sensor. Because of a special guard ring desig…
We present a multi-layer single-event upset mitigation strategy implemented in a low-cost Xilinx Artix-7 FPGA. The implementation is targeted for a trigger data router for the ATLAS muon spectrometer upgrade. The mitigation strategy employs three layers of protection to improve overall FPGA design robustness: use of triple-modular redundancy for FPGA fabric logic and embedded soft-error mitigation in the first layer; further enhancement with multi-boot FPGA reconfiguration across multiple copies of configuration memory in the second layer; and FPGA power cycling and configuration memory re-ini…
This paper presents the design and test results of a Gigabit Cable Receiver ASIC called GBCR for the HL-LHC upgrade of the ATLAS Inner Tracker (ITk) pixel detector. Three prototypes (GBCR1, GBCR2, and GBCR3) have been designed in the CERN-identified 65 nm CMOS technology. GBCR receives seven (GBCR2) or six (GBCR3) channels (RX) each at 1.28 Gbps from the front-end readout chip RD53B via flex cables up to 1 meter and Twinax cables up to 5 meters and sends the equalized and retimed signals to lpGBT. Both GBCR2 and GBCR3 ASICs have two transmitting channels (TX) that pre-emphasize the signals fro…
A testbeam telescope, based on ATLAS IBL silicon pixel modules, has been built. It comprises six planes of planar silicon sensors with 250 x 50 um^2 pitch, read out by ATLAS FE-I4 chips. In the CERN SPS H8 beamline (180 GeV pi+) a resolution of better than 8 x 12 um^2 at the position of the device under test was achieved. The telescope reached a trigger rate of 6kHz with two measured devices. It is mainly designed for studies using FE-I4 based prototypes, but has also been successfully run with independent DAQ systems. Specialised trigger schemes ensure data synchronisation between these exter…
3D silicon pixel detectors have been investigated as radiation-hard candidates for the innermost layers of the HL-LHC upgrade of the ATLAS pixel detector. 3D detectors are already in use today in the ATLAS IBL and AFP experiments. These are based on 50x250 um2 large pixels connected to the FE-I4 readout chip. Detectors of this generation were irradiated to HL-LHC fluences and demonstrated excellent radiation hardness with operational voltages as low as 180 V and power dissipation of 12--15 mW/cm2 at a fluence of about 1e16 neq/cm2, measured at -25 degree C. Moreover, to cope with the higher oc…
During the shutdown of the CERN Large Hadron Collider in 2013-2014, an additional pixel layer was installed between the existing Pixel detector of the ATLAS experiment and a new, smaller radius beam pipe. The motivation for this new pixel layer, the Insertable B-Layer (IBL), was to maintain or improve the robustness and performance of the ATLAS tracking system, given the higher instantaneous and integrated luminosities realised following the shutdown. Because of the extreme radiation and collision rate environment, several new radiation-tolerant sensor and electronic technologies were utilised…
