Snitch：一种用于浮点密集型工作负载的面积和能量高效执行的微型伪双发布处理器
Snitch: A tiny Pseudo Dual-Issue Processor for Area and Energy Efficient Execution of Floating-Point Intensive Workloads
摘要：
数据分析、机器学习和科学计算等数据并行应用对新兴系统每秒浮点运算的需求不断增长。随着集成密度的增加，对能源效率的追求成为头号设计问题。虽然专用加速器提供了高能效，但它们过于专业化，难以适应算法的变化。我们提出了一个架构概念，解决了实现极端的能源效率的问题，同时仍然保持高灵活性作为一个通用的计算引擎。其关键思想是将一个名为Snitch的小型10 kGE控制核心与一个双精度FPU配对，以调整计算控制比。虽然传统上最大限度地减少非FPU面积和实现高浮点利用率一直是一个权衡，与Snitch，我们实现了这两个，通过增强ISA与两个最小的侵入性扩展：流语义寄存器（SSR）和浮点重复指令（FREP）。SSR允许内核隐式地将加载/存储指令编码为寄存器读/写，从而省略了许多显式的存储器指令。FREP扩展通过对来自微循环缓冲区的指令进行排序来并行处理浮点和整数流水线。这些ISA扩展显著降低了内核的压力，并将其释放给其他任务，使Snitch和FPU有效地以3.2%的最小增量成本双重发布。两个低开销ISA扩展使Snitch比当代向量处理器通道更灵活，实现了$2\times$能效改进。我们已经评估了建议的核心和ISA扩展在22纳米技术的八核集群。我们在多个并行微内核上实现了超过$5\times$的多核加速和$3.5\times$的能效增益。
英文摘要：
Data-parallel applications, such as data analytics, machine learning, and scientific computing, are placing an ever-growing demand on floating-point operations per second on emerging systems. With increasing integration density, the quest for energy efficiency becomes the number one design concern. While dedicated accelerators provide high energy efficiency, they are over-specialized and hard to adjust to algorithmic changes. We propose an architectural concept that tackles the issues of achieving extreme energy efficiency while still maintaining high flexibility as a general-purpose compute engine. The key idea is to pair a tiny 10kGE control core, called Snitch, with a double-precision FPU to adjust the compute to control ratio. While traditionally minimizing non-FPU area and achieving high floating-point utilization has been a trade-off, with Snitch, we achieve them both, by enhancing the ISA with two minimally intrusive extensions: stream semantic registers (SSR) and a floating-point repetition instruction (FREP). SSRs allow the core to implicitly encode load/store instructions as register reads/writes, eliding many explicit memory instructions. The FREP extension decouples the floating-point and integer pipeline by sequencing instructions from a micro-loop buffer. These ISA extensions significantly reduce the pressure on the core and free it up for other tasks, making Snitch and FPU effectively dual-issue at a minimal incremental cost of 3.2%. The two low overhead ISA extensions make Snitch more flexible than a contemporary vector processor lane, achieving a $2\times$ energy-efficiency improvement. We have evaluated the proposed core and ISA extensions on an octa-core cluster in 22nm technology. We achieve more than $5\times$ multi-core speed-up and a $3.5\times$ gain in energy efficiency on several parallel microkernels.
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