Manticore：一种用于超高效浮点计算的4096核RISC-V小芯片架构
Manticore: A 4096-core RISC-V Chiplet Architecture for Ultra-efficient Floating-point Computing
摘要：
数据并行问题要求在严格的面积和能源效率约束下每秒不断增长的浮点（FP）操作。在这项工作中，我们提出了Manticore，一个通用的，超高效的基于芯片的架构，用于数据并行FP工作负载。我们已经在Globalfoundries 22FDX工艺中制造了小芯片计算核心的原型，并证明与CPU和GPU相比，FP密集型工作负载的能源效率提高了5倍以上。高能量和面积效率的计算能力由包含八个小整数核的Snitch集群提供，每个内核控制一个大的FPU。内核支持两个自定义ISA扩展：SSR扩展通过将其编码为寄存器读写来省略显式加载和存储指令。FREP扩展将整数核从FPU中分离出来，允许独立地发出浮点指令。这两个扩展允许单次发出核心最小化其指令获取带宽并使FPU的指令带宽饱和，实现超过90%的FPU利用率，其中超过40%的核心区域专用于FPU。
英文摘要：
Data-parallel problems demand ever growing floating-point (FP) operations per second under tight area- and energy-efficiency constraints. In this work, we present Manticore, a general-purpose, ultra-efficient chiplet-based architecture for data-parallel FP workloads. We have manufactured a prototype of the chiplet's computational core in Globalfoundries 22FDX process and demonstrate more than 5x improvement in energy efficiency on FP intensive workloads compared to CPUs and GPUs. The compute capability at high energy and area efficiency is provided by Snitch clusters containing eight small integer cores, each controlling a large FPU. The core supports two custom ISA extensions: The SSR extension elides explicit load and store instructions by encoding them as register reads and writes. The FREP extension decouples the integer core from the FPU allowing floating-point instructions to be issued independently. These two extensions allow the single-issue core to minimize its instruction fetch bandwidth and saturate the instruction bandwidth of the FPU, achieving FPU utilization above 90%, with more than 40% of core area dedicated to the FPU.
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