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arXiv 1909.09165quant-phcond-mat.mes-hallphysics.app-ph
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超导量子相干电路中圆片级约瑟夫森结电阻变化的改善

Improving wafer-scale Josephson junction resistance variation in superconducting quantum coherent circuits

J. M. Kreikebaum, K. P. O'Brien, A. Morvan, I. Siddiqi

摘要:

量子比特(quantum bits)是下一代计算机和探测器所设想的相干电路的一个例子。具有$O$(100 $μ$ s)的相干寿命的鲁棒超导量子比特是transmon:约瑟夫森结用作与电容器并联以形成非谐振子的非线性电感器。在具有许多这种传输子的复杂器件中,通常需要对每个量子比特频率进行精确控制,因此结面积和隧道势垒厚度的变化必须充分最小化,以实现最佳性能,同时避免相邻电路之间的光谱重叠。简单地将我们针对单个独立器件优化的配方移植到晶圆级(从150 mm晶圆生产64,1x1 cm管芯),最初导致室温隧穿电阻的全局漂移为$\pm$ 30%。推断从这个电阻分布的临界电流$I_{\rm c}$的变化,我们提出了一个优化的过程,从系统的38个晶片的研究,结果在$<$ 3.5%的相对标准偏差(RSD)的临界电流($\equiv σ_{I_{\rm c}}/\left\langle I_{\rm c} \right\rangle$)为3000约瑟夫森结(单结和非对称SQUID)在49厘米$^2$。在衬底上的1x1 cm移动窗口内观察给出了给定量子位芯片的变化特性的估计。我们的最佳工艺,利用超声辅助显影、均匀灰化和动态氧化,显示平均在1x1 cm内$σ_{I_{\rm c}}/\left\langle I_{\rm c} \right\rangle$ = 1.8%,少数1x1 cm区域的$σ_{I_{\rm c}}/\left\langle I_{\rm c} \right\rangle$ $<$ 1.0%(相当于$σ_{f}/\left\langle f \right\rangle$ $<$ 0.5%)。这种稳定性将大大提高具有严格临界电流要求的多结芯片的产量。

英文摘要:

Quantum bits, or qubits, are an example of coherent circuits envisioned for next-generation computers and detectors. A robust superconducting qubit with a coherent lifetime of $O$(100 $μ$s) is the transmon: a Josephson junction functioning as a non-linear inductor shunted with a capacitor to form an anharmonic oscillator. In a complex device with many such transmons, precise control over each qubit frequency is often required, and thus variations of the junction area and tunnel barrier thickness must be sufficiently minimized to achieve optimal performance while avoiding spectral overlap between neighboring circuits. Simply transplanting our recipe optimized for single, stand-alone devices to wafer-scale (producing 64, 1x1 cm dies from a 150 mm wafer) initially resulted in global drifts in room-temperature tunneling resistance of $\pm$ 30%. Inferring a critical current $I_{\rm c}$ variation from this resistance distribution, we present an optimized process developed from a systematic 38 wafer study that results in $<$ 3.5% relative standard deviation (RSD) in critical current ($\equiv σ_{I_{\rm c}}/\left\langle I_{\rm c} \right\rangle$) for 3000 Josephson junctions (both single-junctions and asymmetric SQUIDs) across an area of 49 cm$^2$. Looking within a 1x1 cm moving window across the substrate gives an estimate of the variation characteristic of a given qubit chip. Our best process, utilizing ultrasonically assisted development, uniform ashing, and dynamic oxidation has shown $σ_{I_{\rm c}}/\left\langle I_{\rm c} \right\rangle$ = 1.8% within 1x1 cm, on average, with a few 1x1 cm areas having $σ_{I_{\rm c}}/\left\langle I_{\rm c} \right\rangle$ $<$ 1.0% (equivalent to $σ_{f}/\left\langle f \right\rangle$ $<$ 0.5%). Such stability would drastically improve the yield of multi-junction chips with strict critical current requirements.

机构、总结、中文摘要均由AI分析而来,可能存在错误,请以论文正文为准。

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