Intensive computation is entering data centers with multiple workloads of deep learning. To balance the compute efficiency, performance, and total cost of ownership (TCO), the use of a field-programmable gate array (FPGA) with reconfigurable logic provides an acceptable acceleration capacity and is compatible with diverse computation-sensitive tasks in the cloud. In this paper, we develop an FPGA acceleration platform that leverages a unified framework architecture for general-purpose convolutional neural network (CNN) inference acceleration at a data center. To overcome the computation bound, 4,096 DSPs are assembled and shaped as supertile units (SUs) for different types of convolution, which provide up to 4.2 TOP/s 16-bit fixed-point performance at 500 MHz. The interleaved-task-dispatching method is proposed to map the computation across the SUs, and the memory bound is solved by a dispatching-assembling buffering model and broadcast caches. For various non-convolution operators, a filter processing unit is designed for general-purpose filter-like/pointwise operators. In the experiment, the performances of CNN models running on server-class CPUs, a GPU, and an FPGA are compared. The results show that our design achieves the best FPGA peak performance and a throughput at the same level as that of the state-of-the-art GPU in data centers, with more than 50 times lower latency.
Auto-ViT-Acc: An FPGA-Aware Automatic Acceleration Framework for Vision Transformer with Mixed-Scheme Quantization
Northeastern University（东北大学）；Simon Fraser University（西蒙弗雷泽大学）；University of California, Irvine（加州大学欧文分校）；ETH Zurich（苏黎世联邦理工学院）；The University of Texas at Austin（德克萨斯大学奥斯汀分校）
视觉Transformer（ViT）正在出现，在计算机视觉任务中具有显著提高的准确性。然而，其复杂的体系结构和巨大的计算/存储需求迫切需要新的硬件加速器的设计方法。这项工作提出了一个FPGA感知的自动ViT加速框架的基础上提出的混合方案量化。据我们所知，这是第一个基于FPGA的ViT加速框架，探索模型量化。与最先进的ViT量化工作（算法方法，只有没有硬件加速）相比，我们的量化实现了0.47%至1.36%的高的Top-1精度在相同的位宽。与32位浮点基线FPGA加速器相比，我们的加速器的帧速率提高了约5.6倍（即，56.8 FPS vs. 10.0 FPS），DeiT-base在ImageNet数据集上的准确率下降了0.71%。
Fast convolutional neural networks on FPGAs with hls4ml
European Organization for Nuclear Research (CERN)（欧洲核子研究组织）；Institute of Physics Belgrade（贝尔格莱德物理研究所）；Politecnico di Milano（米兰理工大学）；California Institute of Technology（加州理工学院）；Chalmers University of Technology（查尔姆斯理工大学）；Zenseact（Zenseact公司）；ICEPP, University of Tokyo（东京大学国际基本粒子物理研究所）；Columbia University（哥伦比亚大学）；University of California San Diego（加州大学圣地亚哥分校）；Massachusetts Institute of Technology（麻省理工学院）；Fermi National Accelerator Laboratory（费米国家加速器实验室）；Purdue University（普渡大学）；HawkEye360（鹰眼360公司）；University of Illinois at Chicago（伊利诺伊大学芝加哥分校）；Rhodes College（罗德学院）
BearingPGA-Net: A Lightweight and Deployable Bearing Fault Diagnosis Network via Decoupled Knowledge Distillation and FPGA Acceleration
Harbin Institute of Technology（哈尔滨工业大学）；The Hong Kong Polytechnic University（香港理工大学）；Analog Devices, Inc.（亚德诺公司）；The Chinese University of Hong Kong（香港中文大学）
Enabling Vibration-Based Gesture Recognition on Everyday Furniture via Energy-Efficient FPGA Implementation of 1D Convolutional Networks
1 Ubiquitous Computing Systems Laboratory, Nara Institute of Science；Technology, Nara, Japan 2 Intelligent Embedded Systems Laboratory, University of Duisburg-Essen, Duisburg, Germany 3 PALUNO, The Ruhr Institute for Software Technology, Essen, Germany 4 RIKEN, Center for Advanced Intelligence Project, Tokyo, Japan
A GPU-Outperforming FPGA Accelerator Architecture for Binary Convolutional Neural Networks
Arizona State University（亚利桑那州立大学）；Nanyang Technological University（南洋理工大学）
基于FPGA的卷积神经网络（CNN）硬件加速器由于其比GPU更高的能量效率而受到广泛关注。然而，基于FPGA的解决方案要实现比GPU更高的吞吐量是具有挑战性的。在本文中，我们证明了当CNN在权重和激活的二进制约束下进行训练时，FPGA加速在吞吐量和能效方面都是一种优越的解决方案。具体来说，我们提出了一种优化的FPGA加速器架构，专为逐位卷积和归一化而设计，具有大规模的空间并行性和深流水线阶段。FPGA加速器的一个关键优势是其性能对数据批量大小不敏感，而GPU加速的性能在很大程度上取决于数据的批量大小。实验结果表明，在Virtex-7 FPGA上运行的二进制CNN的加速器架构比Titan X GPU快8.3倍，能效高75倍，可以处理小批量的在线个人请求。对于处理大批量静态数据，该解决方案在吞吐量方面与Titan X GPU不相上下，同时提供9.5倍的能效。
Towards Efficient Convolutional Neural Network for Domain-Specific Applications on FPGA
Imperial College London（帝国理工学院）；Corerain Technologies Ltd.（鲲云科技有限公司）
FPGA是近年来实现卷积神经网络（CNN）的热门技术。FPGA上的大多数CNN应用程序都是特定于领域的，例如从特定类别中检测对象，其中在一般数据集上预训练的常用CNN模型可能不够有效。TuRF是一个端到端的CNN加速框架，通过迁移学习在FPGA上高效地部署特定领域的应用，将预训练模型适应特定领域，用高效的卷积块替换标准卷积层，并应用层融合来增强硬件设计性能。我们通过在Stratix V FPGA上部署用于特定领域图像识别任务的预训练VGG-16模型来评估TuRF。结果表明，对于原始VGG-16和ResNet-50模型，TuRF生成的设计比以前的方法实现了更好的性能，而对于优化的VGG-16模型，TuRF设计更准确，更容易处理。
Hardware acceleration for ultra-fast Neural Network training on FPGA for MRF map reconstruction
National Institute of Nuclear Physics (INFN), Division of Bologna（国家核物理研究所（INFN），博洛尼亚分校）；National Institute of Nuclear Physics (INFN), Division of Pisa（国家核物理研究所（INFN），比萨分校）
FPGA-based Accelerators of Deep Learning Networks for Learning and Classification: A Review
Department of Computer Engineering, King Fahd University of Petroleum \& Minerals, Dhahran-31261, Saudi Arabia；Center for Communications；IT Research, Research Institute, King Fahd University of Petroleum \& Minerals, Dhahran-31261, Saudi Arabia
Comprehensive Evaluation of OpenCL-based Convolutional Neural Network Accelerators in Xilinx and Altera FPGAs
Robotic and Technology of Computers Lab（机器人及计算机技术实验室）；School of Electrical, Computer and Energy Engineering（电气、计算机与能源工程学院）；University of Seville（塞维利亚大学）；Arizona State University（亚利桑那州立大学）
Towards Design Space Exploration and Optimization of Fast Algorithms for Convolutional Neural Networks (CNNs) on FPGAs
Syed Babar Ali School of Science and Engineering (SBASSE), Lahore University of Management Sciences (LUMS)（拉合尔管理科学大学赛义德·巴巴尔·阿里理工学院（SBASSE））；Department of Electrical Engineering, Syed Babar Ali School of Science and Engineering (SBASSE), Lahore University of Management Sciences (LUMS)（拉合尔管理科学大学赛义德·巴巴尔·阿里理工学院电气工程系（SBASSE））；Lahore University of Management Sciences (LUMS)（拉合尔管理科学大学（LUMS））；Department of Electrical Engineering（电气工程系）
