ZynqNet：FPGA加速的嵌入式卷积神经网络
ZynqNet: An FPGA-Accelerated Embedded Convolutional Neural Network
摘要：
图像理解正在成为从医疗诊断到自动驾驶汽车等越来越多应用的重要功能。许多应用需要嵌入式解决方案，这些解决方案可以集成到具有严格实时性和功耗限制的现有系统中。卷积神经网络（CNN）目前在所有图像理解基准中都达到了破纪录的精度，但具有非常高的计算复杂性。因此，嵌入式CNN需要小而高效，但功能非常强大的计算平台。本硕士论文探讨了基于FPGA的CNN加速的潜力，并演示了Zynq片上系统上的全功能概念验证CNN实现。ZynqNet嵌入式CNN专为ImageNet上的图像分类而设计，由ZynqNet CNN（一种优化和定制的CNN拓扑）和ZynqNet FPGA加速器（一种用于评估的基于FPGA的架构）组成。ZynqNet CNN是一种高效的CNN拓扑。使用定制设计的Netscope CNN分析器对现有拓扑结构进行详细分析和优化，使CNN具有84.5%的前5名准确度，计算复杂性仅为5.3亿次乘法累加运算。该拓扑高度规则，仅由卷积层、ReLU非线性和一个全局池化层组成。CNN非常适合FPGA加速器。ZynqNet FPGA加速器允许对ZynqNet CNN进行高效评估。它基于嵌套循环算法加速整个网络，最大限度地减少算术运算和内存访问的数量。FPGA加速器已使用Xilinx Zynq XC-7Z 045的高级综合进行综合，并达到200 MHz的时钟频率，器件利用率为80%至90%。
英文摘要：
Image Understanding is becoming a vital feature in ever more applications ranging from medical diagnostics to autonomous vehicles. Many applications demand for embedded solutions that integrate into existing systems with tight real-time and power constraints. Convolutional Neural Networks (CNNs) presently achieve record-breaking accuracies in all image understanding benchmarks, but have a very high computational complexity. Embedded CNNs thus call for small and efficient, yet very powerful computing platforms. This master thesis explores the potential of FPGA-based CNN acceleration and demonstrates a fully functional proof-of-concept CNN implementation on a Zynq System-on-Chip. The ZynqNet Embedded CNN is designed for image classification on ImageNet and consists of ZynqNet CNN, an optimized and customized CNN topology, and the ZynqNet FPGA Accelerator, an FPGA-based architecture for its evaluation. ZynqNet CNN is a highly efficient CNN topology. Detailed analysis and optimization of prior topologies using the custom-designed Netscope CNN Analyzer have enabled a CNN with 84.5% top-5 accuracy at a computational complexity of only 530 million multiplyaccumulate operations. The topology is highly regular and consists exclusively of convolutional layers, ReLU nonlinearities and one global pooling layer. The CNN fits ideally onto the FPGA accelerator. The ZynqNet FPGA Accelerator allows an efficient evaluation of ZynqNet CNN. It accelerates the full network based on a nested-loop algorithm which minimizes the number of arithmetic operations and memory accesses. The FPGA accelerator has been synthesized using High-Level Synthesis for the Xilinx Zynq XC-7Z045, and reaches a clock frequency of 200MHz with a device utilization of 80% to 90 %.
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
