面向专用片上网络的广义容错拓扑生成
Generalized Fault-Tolerance Topology Generation for Application Specific Network-on-Chips
摘要：
片上网络是解决众核处理器和神经网络处理器中通信瓶颈的一个很有前途的候选方案。在这项工作中，我们考虑的广义容错拓扑生成问题，其中的链路或交换机故障可能发生，为特定应用的片上网络（ASNoC）。与用户定义的数字，K，我们提出了一个整数线性规划（ILP）为基础的方法来生成ASNoC拓扑结构，它可以容忍最多K个故障的开关或链路。鉴于核心之间的通信要求和他们的平面图，我们首先提出了一个凸成本流为基础的方法来解决核心映射问题的核心和交换机之间建立连接。其次，提出了一种基于ILP的方法，为核之间的每个通信流分配K+1个交换机不相交的路由路径。最后，为了减少交换机的大小，我们提出了共享交换机端口的核心和交换机之间的连接，并制定了一个分区问题的端口共享问题。此外，我们提出了一个基于ILP的方法，同时解决核心映射和路由路径分配问题时，只考虑物理链路故障。实验结果表明，由于路由路径的冗余，容错拓扑的功耗几乎随K线性增加。当同时考虑交换机故障和链路故障时，端口共享可以使K = 1、K = 2和K = 3的容错拓扑的平均功耗分别降低18.08%、28.88%和34.20%。实验结果表明，在仅考虑物理链路故障的情况下，与FTTG算法相比，该方法的功耗和跳数分别降低了10.58%和6.25%，与基于DBG的方法相比，该方法的功耗和跳数分别降低了21.72%和9.35%。
英文摘要：
The Network-on-Chips is a promising candidate for addressing communication bottlenecks in many-core processors and neural network processors. In this work, we consider the generalized fault-tolerance topology generation problem, where the link or switch failures can happen, for application-specific network-on-chips (ASNoC). With a user-defined number, K, we propose an integer linear programming (ILP) based method to generate ASNoC topologies, which can tolerate at most K faults in switches or links. Given the communication requirements between cores and their floorplan, we first propose a convex-cost-flow based method to solve a core mapping problem for building connections between the cores and switches. Second, an ILP based method is proposed to allocate K+1 switch-disjoint routing paths for every communication flow between the cores. Finally, to reduce switch sizes, we propose sharing the switch ports for the connections between the cores and switches and formulate the port sharing problem as a clique-partitioning problem Additionally, we propose an ILP-based method to simultaneously solve the core mapping and routing path allocation problems when considering physical link failures only. Experimental results show that the power consumptions of fault-tolerance topologies increase almost linearly with K because of the routing path redundancy. When both switch faults and link faults are considered, port sharing can reduce the average power consumption of fault-tolerance topologies with K = 1, K = 2 and K = 3 by 18.08%, 28.88%, and 34.20%, respectively. When considering only the physical link faults, the experimental results show that compared to the FTTG algorithm, the proposed method reduces power consumption and hop count by 10.58% and 6.25%, respectively; compared to the DBG based method, the proposed method reduces power consumption and hop count by 21.72% and 9.35%, respectively.
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