自适应三维IC TSV容错结构生成
Adaptive 3D-IC TSV Fault Tolerance Structure Generation
摘要：
在三维集成电路（3D-IC）中，硅通孔（TSV）是提供垂直连接的关键技术。然而，成品率和可靠性是基于TSV的3D-IC技术在工业上采用的关键障碍之一。为了提高成品率和可靠性，文献中已经提出了使用备用TSV来修复故障功能TSV的各种容错结构，但是由于缺乏用于容错结构的有效生成方法，不能总是找到有效的结构。在本文中，我们专注于自适应容错结构生成问题。给定功能TSV和备用TSV之间的关系，我们首先计算每个TSV组中的最大容许故障数。然后，我们提出了一个整数线性规划（ILP）为基础的模型，以最小的复用器延迟开销和硬件成本的自适应容错结构。我们进一步开发了一个加速技术，通过有效的最小成本最大流（MCMF）模型。所有提出的方法都被嵌入到一个自顶向下的TSV规划框架中，以形成功能TSV组并生成自适应容错结构。实验结果表明，与现有技术相比，可以有效地减少用于容错的备用TSV的数量。
英文摘要：
In three dimensional integrated circuits (3D-ICs), through silicon via (TSV) is a critical technique in providing vertical connections. However, the yield and reliability is one of the key obstacles to adopt the TSV based 3D-ICs technology in industry. Various fault-tolerance structures using spare TSVs to repair faulty functional TSVs have been proposed in literature for yield and reliability enhancement, but a valid structure cannot always be found due to the lack of effective generation methods for fault-tolerance structures. In this paper, we focus on the problem of adaptive fault-tolerance structure generation. Given the relations between functional TSVs and spare TSVs, we first calculate the maximum number of tolerant faults in each TSV group. Then we propose an integer linear programming (ILP) based model to construct adaptive fault-tolerance struc- ture with minimal multiplexer delay overhead and hardware cost. We further develop a speed-up technique through efficient min-cost-max-flow (MCMF) model. All the proposed method- ologies are embedded in a top-down TSV planning framework to form functional TSV groups and generate adaptive fault- tolerance structures. Experimental results show that, compared with state-of-the-art, the number of spare TSVs used for fault tolerance can be effectively reduced.
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