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arXiv 1806.09207physics.ins-dethep-ex
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用于ATLAS喷射量热计触发系统的新型高速Ultrascale+板

A new high speed, Ultrascale+ based board for the ATLAS jet calorimeter trigger system

B. Bauss, A. Brogna, V. Bücher, J. Damp, R. Degele, H. Herr, C. Kahra, S. Rave, E. Rocco, U. Schäfer, J. Souza, D. B. Ta, S. Tapprogge, M. Weirich

摘要:

为了应对2021年大型强子对撞机(LHC)的亮度增强,ATLAS合作计划进行重大探测器升级。作为其中的一部分,基于量热计数据的1级触发器将升级,以利用新的特征提取器(FEX)系统进行细粒度读取,每个系统都为触发器选择重建不同的物理对象。射流FEX(jFEX)系统旨在提供射流识别(包括大面积射流)和在小于400 ns的延迟预算内测量全局变量。它由6个模块组成。单个jFEX模块是一个ATCA板,配有4个Xilinx Ultrascale+系列的大型FPGA,可使用多达120个多千兆收发器(MGT)、24个电光器件、夹层板控制和电源,消化约3.6 Tb/s的总输入数据速率,从而在不影响主板的情况下灵活升级控制功能和组件。精心设计的24层堆叠结构可在非常密集的高速信号板中保持信号完整性,并选择MEGTRON 6作为最合适的PCB材料。本文报告了jFEX原型的设计挑战和测试结果。特别是完全组装的最终原型已经在内部和CERN的综合测试中测试了高达12.8 Gb/s。完整的jFEX系统将于2018年底生产,以便在2021年3月LHC重启之前完成安装和调试。

英文摘要:

To cope with the enhanced luminosity at the Large Hadron Collider (LHC) in 2021, the ATLAS collaboration is planning a major detector upgrade. As a part of this, the Level 1 trigger based on calorimeter data will be upgraded to exploit the fine granularity readout using a new system of Feature EXtractors (FEX), which each reconstruct different physics objects for the trigger selection. The jet FEX (jFEX) system is conceived to provide jet identification (including large area jets) and measurements of global variables within a latency budget of less then 400ns. It consists of 6 modules. A single jFEX module is an ATCA board with 4 large FPGAs of the Xilinx Ultrascale+ family, that can digest a total input data rate of ~3.6 Tb/s using up to 120 Multi Gigabit Transceiver (MGT), 24 electrical optical devices, board control and power on the mezzanines to allow flexibility in upgrading controls functions and components without affecting the main board. The 24-layers stack-up was carefully designed to preserve the signal integrity in a very densely populated high speed signal board selecting MEGTRON6 as the most suitable PCB material. This contribution reports on the design challenges and the test results of the jFEX prototypes. In particular the fully assembled final prototype has been tested up to 12.8 Gb/s in house and in integrated tests at CERN. The full jFEX system will be produced by the end of 2018 to allow for installation and commissioning to be completed before LHC restarts in March 2021.

机构、总结、中文摘要均由AI分析而来,可能存在错误,请以论文正文为准。

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