FPGA加速在ADC性能标定中的应用
Application of FPGA Acceleration in ADC Performance Calibration
摘要：
近年来，高速、高分辨率的模数转换器（ADC）在许多物理实验中得到了广泛的应用，特别是在高精度的时间和电荷测量中。数字化数据量的快速增长需要更快的计算速度。FPGA加速以其流处理和并行处理的特点在数据处理中有着诱人的应用前景。介绍了一种基于FPGA加速的ADC性能校准应用。FPGA从PC存储器中读取ADC数字化数据流，进行处理，然后将处理结果写回PC存储器。采用PCIE总线提高数据传输速度，采用浮点算法提高精度。测试结果表明，与传统的基于C语言的CPU处理方法相比，FPGA加速可以减少ADC性能校准的处理时间。该框架基于PCIe的FPGA加速方法可应用于未来大型ADC阵列物理实验的分析和仿真，如CCD摄像机和波形数字化读出电子学校准。
英文摘要：
In recent years, high speed and high resolution analog-to-digital converter (ADC) is widely employed in many physical experiments, especially in high precision time and charge measurement. The rapid increasing amount of digitized data demands faster computing. FPGA acceleration has an attracting prospect in data process for its stream process and parallel process feature. In this paper, an ADC performance calibration application based on FPGA acceleration is described. FPGA reads the ADC digitized data stream from PC memory, processes and then writes processed result back to the PC memory. PCIE bus is applied to increase the data transfer speed, and floating point algorithm is applied to improve the accuracy. The test result shows that FPGA acceleration can reduce the processing time of the ADC performance calibration compared with traditional method of C-based CPU processing. This frame of PCIE-based FPGA acceleration method can be applied in analysis and simulation in the future physical experiment for large ADC array, such as CCD camera and waveform digitization readout electronics calibration.
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