流水线ADC级非理想性的均匀性强制校准
Homogeneity Enforced Calibration of Stage Nonidealities for Pipelined ADCs
摘要：
流水线模数转换器（ADC）是要求高采样率和高线性度的各种信号处理系统的基本部件。在过去的几年里，校准技术已被深入研究，以提高线性度。在这项工作中，我们提出了一个均衡为基础的校准技术，不需要知识的ADC输入信号进行校准。为此，测试信号及其缩放版本被依次馈入ADC，而只有相应的输出样本用于校准。有几种测试信号源是可能的，例如信号发生器（SG）或系统应用（SA）本身。对于后一种情况，所提出的方法对应于背景校准技术。因此，缓慢变化的误差被连续地跟踪和校准。由于校准技术的计算复杂度较低，因此适合片上实现。最后，这项工作包含的稳定性和收敛行为以及仿真结果的分析。
英文摘要：
Pipelined analog-to-digital converters (ADCs) are fundamental components of various signal processing systems requiring high sampling rates and a high linearity. Over the past years, calibration techniques have been intensively investigated to increase the linearity. In this work, we propose an equalization-based calibration technique which does not require knowledge of the ADC input signal for calibration. For that, a test signal and a scaled version of it are fed into the ADC sequentially, while only the corresponding output samples are used for calibration. Several test signal sources are possible, such as a signal generator (SG) or the system application (SA) itself. For the latter case, the presented method corresponds to a background calibration technique. Thus, slowly changing errors are tracked and calibrated continuously. Because of the low computational complexity of the calibration technique, it is suitable for an on-chip implementation. Ultimately, this work contains an analysis of the stability and convergence behavior as well as simulation results.
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
