基于SRAM的FPGA三模冗余划分的可靠性建模与优化
Dependability modeling and optimization of triple modular redundancy partitioning for SRAM-based FPGAs
摘要：
基于SRAM的FPGA因其现场可编程性和低成本而在航空航天工业中很受欢迎。然而，它们遭受宇宙辐射引起的单粒子翻转（SEU）。三重模块冗余（TMR）是一种用于减轻FPGA中的SEU的众所周知的技术，其通常与另一种称为配置清理的SEU减轻技术一起使用。传统的TMR一次提供针对单个故障的保护，而分区的TMR提供改进的可靠性和可用性。在本文中，我们提出了一种方法来分析TMR划分在早期的设计阶段，使用概率模型检验。所提出的正式模型可以捕获单细胞和多细胞的颠覆情况下，无论任何假设的分区大小相等。从设计的高级描述开始，使用指定数量的分区、组件表征库和用户定义的擦洗速率从数据流图（DFG）构建马尔可夫模型。这样的模型和详尽的分析捕获了辐射环境中系统中可能发生的所有故障和维修。然后，使用PRISM模型检查器自动验证各种可靠性和可用性属性，探索擦洗频率和满足设计要求所需的TMR分区数量之间的关系。此外，报告的结果表明，基于已知的投票失败率，它是可能的，找到一个最佳的分区数在早期设计阶段，使用我们提出的方法。
英文摘要：
SRAM-based FPGAs are popular in the aerospace industry for their field programmability and low cost. However, they suffer from cosmic radiation-induced Single Event Upsets (SEUs). Triple Modular Redundancy (TMR) is a well-known technique to mitigate SEUs in FPGAs that is often used with another SEU mitigation technique known as configuration scrubbing. Traditional TMR provides protection against a single fault at a time, while partitioned TMR provides improved reliability and availability. In this paper, we present a methodology to analyze TMR partitioning at early design stage using probabilistic model checking. The proposed formal model can capture both single and multiple-cell upset scenarios, regardless of any assumption of equal partition sizes. Starting with a high-level description of a design, a Markov model is constructed from the Data Flow Graph (DFG) using a specified number of partitions, a component characterization library and a user defined scrub rate. Such a model and exhaustive analysis captures all the considered failures and repairs possible in the system within the radiation environment. Various reliability and availability properties are then verified automatically using the PRISM model checker exploring the relationship between the scrub frequency and the number of TMR partitions required to meet the design requirements. Also, the reported results show that based on a known voter failure rate, it is possible to find an optimal number of partitions at early design stages using our proposed method.
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