大气辐射下UltraScale + MPSoC系统的单粒子效应评估
Single Event Effects Assessment of UltraScale+ MPSoC Systems under Atmospheric Radiation
摘要：
AMD UltraScale+ XCZU 9 EG器件是一款具有嵌入式可编程逻辑（PL）的多处理器片上系统（MPSoC），在许多边缘（例如，汽车或航空电子设备）和云（例如，数据中心）地面应用。然而，它包含大量SRAM单元，使器件容易受到中子诱发单粒子翻转（NSEU）或其他软错误的影响。半导体供应商结合了软错误减轻机制来恢复存储器扰乱（即，错误），然后才传播到应用程序输出并成为错误。但是MPSoC的缓解方案有多有效？在不同的工作负载下，它们能否有效地恢复高海拔或大规模应用中的干扰？本文通过加速中子辐射试验和可靠性分析，回答了上述研究问题。我们在广泛的工作负载上测试了该设备，例如用于姿态估计和天气预测的多线程软件或在AMD深度学习处理单元（DPU）上运行的软件/硬件（SW/HW）协同设计图像分类应用程序。假设在纽约市（NYC）的40 k英尺处的单节点MPSoC系统，所有测试的软件应用实现大于148个月的平均故障时间（MTTF），这表明在MPSoC的处理系统中有效地恢复了扰乱。然而，软件/硬件协同设计（即，DPU）在40 k英尺的同一个单节点系统中的MTTF = 4个月，这是由于其PL加速器的高故障率，这强调了一些MPSoC工作负载可能需要额外的NSEU缓解方案。尽管如此，我们表明，MTTF的DPU可以增加到87个月，没有任何开销，如果一个忽视的故障率的可容忍的错误，因为它们不影响分类输出的正确性。
英文摘要：
The AMD UltraScale+ XCZU9EG device is a Multi-Processor System-on-Chip (MPSoC) with embedded Programmable Logic (PL) that excels in many Edge (e.g., automotive or avionics) and Cloud (e.g., data centres) terrestrial applications. However, it incorporates a large amount of SRAM cells, making the device vulnerable to Neutron-induced Single Event Upsets (NSEUs) or otherwise soft errors. Semiconductor vendors incorporate soft error mitigation mechanisms to recover memory upsets (i.e., faults) before they propagate to the application output and become an error. But how effective are the MPSoC's mitigation schemes? Can they effectively recover upsets in high altitude or large scale applications under different workloads? This article answers the above research questions through a solid study that entails accelerated neutron radiation testing and dependability analysis. We test the device on a broad range of workloads, like multi-threaded software used for pose estimation and weather prediction or a software/hardware (SW/HW) co-design image classification application running on the AMD Deep Learning Processing Unit (DPU). Assuming a one-node MPSoC system in New York City (NYC) at 40k feet, all tested software applications achieve a Mean Time To Failure (MTTF) greater than 148 months, which shows that upsets are effectively recovered in the processing system of the MPSoC. However, the SW/HW co-design (i.e., DPU) in the same one-node system at 40k feet has an MTTF = 4 months due to the high failure rate of its PL accelerator, which emphasises that some MPSoC workloads may require additional NSEU mitigation schemes. Nevertheless, we show that the MTTF of the DPU can increase to 87 months without any overhead if one disregards the failure rate of tolerable errors since they do not affect the correctness of the classification output.
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
