Probabilistic spin logic (PSL) is a recently proposed computing paradigm based on unstable stochastic units called probabilistic bits (p-bits) that can be correlated to form probabilistic circuits (p-circuits). These p-circuits can be used to solve problems of optimization, inference and also to implement precise Boolean functions in an "inverted" mode, where a given Boolean circuit can operate in reverse to find the input combinations that are consistent with a given output. In this paper we present a scalable FPGA implementation of such invertible p-circuits. We implement a "weighted" p-bit that combines stochastic units with localized memory structures. We also present a generalized tile of weighted p-bits to which a large class of problems beyond invertible Boolean logic can be mapped, and how invertibility can be applied to interesting problems such as the NP-complete Subset Sum Problem by solving a small instance of this problem in hardware.
Department of Electrical and Computer Engineering, University of California, Santa Barbara（加州大学圣芭芭拉分校电气与计算机工程系）；Radboud University, Institute for Molecules and Materials（拉德堡德大学分子与材料研究所）；University of California, Santa Barbara（加州大学圣芭芭拉分校）
Spin Vector Control for Heisenberg-Inspired Probabilistic Computing
Purdue University（普渡大学）；Birck Nanotechnology Center, Purdue University（普渡大学比尔克纳米技术中心）；University of California, Santa Barbara（加州大学圣塔芭芭拉分校）；King Fahd University of Petroleum & Minerals (KFUPM)（法赫德国王石油与矿产大学）
CMOS + stochastic nanomagnets: heterogeneous computers for probabilistic inference and learning
University of California Santa Barbara（加州大学圣巴巴拉分校）；Tohoku University（东北大学）；Research Institute of Electrical Communication, Tohoku University（东北大学电气通信研究所）；Graduate School of Engineering, Tohoku University（东北大学工学研究科）
