自治贝叶斯网络的硬件设计
Hardware Design for Autonomous Bayesian Networks
摘要：
在许多AI相关领域中流行的用于概率推理和因果推理的有向非循环图或贝叶斯网络可以映射到由概率比特（p比特）构建的概率电路，类似于随机人工神经网络的二进制随机神经元。为了满足标准的统计结果，各个p位不仅需要顺序地更新，而且还需要从父节点到子节点的顺序更新，这使得在软件实现中必须使用定序器。在本文中，我们首先使用SPICE模拟来证明自主硬件贝叶斯网络可以在没有任何时钟或定序器的情况下正确运行，但前提是各个p位被适当设计。然后，我们提出了一个简单的行为模型的自主硬件说明正确的无序列操作所需的基本特征。该模型也对SPICE模拟进行了基准测试，可用于模拟大规模网络。我们的研究结果可能是有用的硬件加速器的设计，使用节能的构建块适合低层次的实现贝叶斯网络。我们提出的随机硬件的自主大规模并行操作具有生物相关性，因为大脑中的神经动力学本质上也是随机和自主的。
英文摘要：
Directed acyclic graphs or Bayesian networks that are popular in many AI related sectors for probabilistic inference and causal reasoning can be mapped to probabilistic circuits built out of probabilistic bits (p-bits), analogous to binary stochastic neurons of stochastic artificial neural networks. In order to satisfy standard statistical results, individual p-bits not only need to be updated sequentially, but also in order from the parent to the child nodes, necessitating the use of sequencers in software implementations. In this article, we first use SPICE simulations to show that an autonomous hardware Bayesian network can operate correctly without any clocks or sequencers, but only if the individual p-bits are appropriately designed. We then present a simple behavioral model of the autonomous hardware illustrating the essential characteristics needed for correct sequencer-free operation. This model is also benchmarked against SPICE simulations and can be used to simulate large scale networks. Our results could be useful in the design of hardware accelerators that use energy efficient building blocks suited for low-level implementations of Bayesian networks. The autonomous massively parallel operation of our proposed stochastic hardware has biological relevance since neural dynamics in brain is also stochastic and autonomous by nature.
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
