基于标准6 T SRAM阵列的481 pJ/decision 3.4M decision/s多功能存储器内深推理处理器
A 481pJ/decision 3.4M decision/s Multifunctional Deep In-memory Inference Processor using Standard 6T SRAM Array
摘要：
本文介绍了一种多功能的深在内存处理器的推理应用。通过将间距匹配的低SNR模拟处理嵌入到65 nm CMOS中的标准6 T 16 KB SRAM阵列中，实现了深度内存处理。展示了四个应用程序。与传统架构相比，该原型在所有四种应用中实现了高达5.6倍（多银行场景估计为9.7倍）的节能，精度下降可忽略不计（<1%）。
英文摘要：
This paper describes a multi-functional deep in-memory processor for inference applications. Deep in-memory processing is achieved by embedding pitch-matched low-SNR analog processing into a standard 6T 16KB SRAM array in 65 nm CMOS. Four applications are demonstrated. The prototype achieves up to 5.6X (9.7X estimated for multi-bank scenario) energy savings with negligible (<1%) accuracy degradation in all four applications as compared to the conventional architecture.
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
