用于减轻相变存储器中的写入干扰的模块内干扰屏障
An In-Module Disturbance Barrier for Mitigating Write Disturbance in Phase-Change Memory
摘要：
写干扰错误（WDE）作为一个严重的可靠性问题出现，阻止相变存储器（PCM）的一般商业化，因此已经提出了一些研究来减轻WDE。验证和校正（VnC）通过在编程后始终验证邻居上的数据正确性来消除WDE，但会产生显著的性能开销。基于编码的方案通过减少易受WDE攻击的数据模式的数量来缓解WDE;然而，缓解性能随应用程序而显著波动。此外，基于编码的方案仍然依赖于基于VNC的方案。基于缓存的方案通过将数据存储在写缓存中来降低WDE，但它需要几兆字节的SRAM来显著减轻WDE。尽管以前的研究的努力，这些方法产生显着的性能或面积开销。因此，一种不依赖于基于VNC的方案或应用程序数据模式的新方法是非常必要的。此外，新方法应该对处理器透明（即，模块内），因为WDE的特性由PCM产品的制造商确定。在本文中，我们提出了一个模块内干扰屏障（IMDB），减轻WDE的需求。IMDB包括两级层次结构，包括两个基于SRAM的表，其条目通过充分利用WDE特性的专用替换策略来管理。简单的替换策略需要在SRAM上有数百个读端口，这在实际硬件中是不可行的，因此，还设计了一个近似比较器。我们还对架构参数进行了严格的探索，以获得具有成本效益的设计。与以前的方法相比，所提出的方法显着减少了WDE，而没有明显的速度下降或额外的能量消耗。
英文摘要：
Write disturbance error (WDE) appears as a serious reliability problem preventing phase-change memory (PCM) from general commercialization, and therefore several studies have been proposed to mitigate WDEs. Verify-and-correction (VnC) eliminates WDEs by always verifying the data correctness on neighbors after programming, but incurs significant performance overhead. Encoding-based schemes mitigate WDEs by reducing the number of WDE-vulnerable data patterns; however, mitigation performance notably fluctuates with applications. Moreover, encoding-based schemes still rely on VnC-based schemes. Cache-based schemes lower WDEs by storing data in a write cache, but it requires several megabytes of SRAM to significantly mitigate WDEs. Despite the efforts of previous studies, these methods incur either significant performance or area overhead. Therefore, a new approach, which does not rely on VnC-based schemes or application data patterns, is highly necessary. Furthermore, the new approach should be transparent to processors (i.e., in-module), because the characteristic of WDEs is determined by manufacturers of PCM products. In this paper, we present an in-module disturbance barrier (IMDB) that mitigates WDEs on demand. IMDB includes a two-level hierarchy comprising two SRAM-based tables, whose entries are managed with a dedicated replacement policy that sufficiently utilizes the characteristics of WDEs. The naive implementation of the replacement policy requires hundreds of read ports on SRAM, which is infeasible in real hardware; hence, an approximate comparator is also designed. We also conduct a rigorous exploration of architecture parameters to obtain a cost-effective design. The proposed method significantly reduces WDEs without noticeable speed degradation or additional energy consumption compared to previous methods.
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