通过并发主机访问实现近数据加速
Near Data Acceleration with Concurrent Host Access
摘要：
与主存集成的近数据加速器（NDA）具有显著的功耗和性能优势。要充分实现这些优势，需要在主机和NDA之间共享大量可用内存容量，以允许某些应用程序进行常规内存访问并使用NDA加速其他应用程序，避免复制数据，实现协作处理，并同时为主机和NDA提供高性能。我们确定并解决了新的挑战，在这种情况下：减轻行本地干扰主机NDA，减少读/写周转开销所造成的细粒度交织的主机和NDA请求，架构的内存布局，支持本地所需的NDA和复杂的地址交织主机性能，并支持分组和传统的内存接口。我们演示了我们的方法在一个模拟的系统，包括一个多核CPU和支持NDA的DDR4内存模块。我们表明，我们的机制，使有效和高效的并发访问使用一组微基准测试，然后展示了潜在的重要的随机方差降低梯度（SVRG）算法的系统。
英文摘要：
Near-data accelerators (NDAs) that are integrated with main memory have the potential for significant power and performance benefits. Fully realizing these benefits requires the large available memory capacity to be shared between the host and the NDAs in a way that permits both regular memory access by some applications and accelerating others with an NDA, avoids copying data, enables collaborative processing, and simultaneously offers high performance for both host and NDA. We identify and solve new challenges in this context: mitigating row-locality interference from host to NDAs, reducing read/write-turnaround overhead caused by fine-grain interleaving of host and NDA requests, architecting a memory layout that supports the locality required for NDAs and sophisticated address interleaving for host performance, and supporting both packetized and traditional memory interfaces. We demonstrate our approach in a simulated system that consists of a multi-core CPU and NDA-enabled DDR4 memory modules. We show that our mechanisms enable effective and efficient concurrent access using a set of microbenchmarks, and then demonstrate the potential of the system for the important stochastic variance-reduced gradient (SVRG) algorithm.
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