一种用于Spartan-6 FPGA的26 ps RMS时间-数字转换器核
A 26 ps RMS time-to-digital converter core for Spartan-6 FPGAs
摘要：
我们已经设计，实施和测试的时间到数字转换器的核心，在一个低成本的斯巴达6 FPGA。我们的设计利用进位链中有限的传播速度来实现延迟线，其中使用数百个抽头来测量传入信号边缘的传播距离。这种技术使内核能够达到远优于FPGA触发器最小开关周期的精度。为了补偿工艺、电压和温度（PVT）效应，我们的设计使用了两种技术的组合：启动校准和在线校准。启动校准使用统计方法来估计延迟线抽头之间的延迟，并有助于消除工艺变化的影响。在线校准在不中断内核操作的情况下进行，使用环形振荡器，其频率不稳定性被测量并用于补偿延迟线上的后续电压和温度效应。测试结果表明，在37 ℃ ~ 48 ℃的温度范围内，该设计达到了26 ps RMS的精度。
英文摘要：
We have designed, implemented and tested a time-to-digital converter core in a low-cost Spartan-6 FPGA. Our design exploits the finite propagation speed in carry chains to realize a delay line in which the propagation distance of the incoming signal's edges is measured using hundreds of taps. This technique enables the core to reach a precision far better than the minimum switching period of the FPGA flip-flops. To compensate for process, voltage and temperature (PVT) effects, our design uses a combination of two techniques: startup calibration and online calibration. The startup calibration uses a statistical method to estimate the delay between the taps of the delay line and helps eliminate the effect of process variations. The online calibration, which takes place without disruption of the core's operation, uses a ring oscillator whose frequency instability is measured and used to compensate for subsequent voltage and temperature effects on the delay line. Our tests show that our design reaches a precision of 26 ps RMS over a temperature range of 37C to 48C.
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
