适用于米级应用系统集成的低功耗3D光子-数字转换器读出电路的特性表征
Characterization of a low-power 3D photon-to-digital converter readout improved for system integration in meter-scale applications
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中文总结 AI 辅助
本研究针对米级应用需求，改进了一款采用台积电180nm工艺的64×64像素ROIC，优化后其定时抖动降低、死时间可调、功耗下降，可集成于PDC用于多领域系统。
中文摘要 AI 辅助
数字硅光电倍增管（dSiPM）是单光子雪崩二极管（SPAD）阵列，每个SPAD都配有独立电子读出电路。为最大化光电探测面积，我们开发了一款读出集成电路（ROIC），将其与Teledyne Dalsa（加拿大布罗蒙）定制设计的SPAD层进行3D集成，形成光子-数字转换器（PDC）。本文展示了一款经改进的ROIC，采用台积电180nm工艺制造，可管理64×64像素架构。该ROIC具备多种输出，包括每当某一像素触发时产生脉冲的标志输出，以及对触发SPAD数量进行采样的数字求和输出。通过优化H树设计，标志输出的定时抖动从72.0ps RMS降至22.6ps RMS；可调保持电路提供32ns至18μs的可调死时间，可同时解决后脉冲抑制及工艺缺陷导致的SPAD间差异问题；通过数字逻辑优化和时钟门控，在触发速率超过10kHz时，功耗降低30%。这些测量结果验证，该ROIC已可用于医疗成像、粒子物理及量子科学领域系统的3D集成，构成PDC。
英文摘要
Digital silicon photomultipliers (dSiPM) are arrays of single photon avalanche diodes (SPADs) where each SPAD has its own electronic readout. To maximize the photodetection area, we developed a readout integrated circuit (ROIC) 3D-integrated to a custom-designed SPAD layer fabricated at Teledyne Dalsa (Bromont, Canada) to form a photon-to-digital converter (PDC). This paper presents an improved version of a previously demonstrated ROIC, fabricated in TSMC 180 nm technology to manage a 64 x 64 pixel architecture. This ROIC has different outputs, such as a flag output that produces a pulse whenever one of the pixels triggers and a digital sum that samples the amount of triggered SPADs. Improvements lead to a reduction of the timing jitter on the flag output from 72.0 ps RMS to 22.6 ps RMS through optimized H-tree design. A tunable hold-off circuit provides adjustable dead time from 32 ns to 18 μs, addressing both afterpulsing mitigation and SPAD-to-SPAD variations due to process defects. Power consumption is lowered by 30% at trigger rates exceeding 10 kHz through digital logic optimization and clock gating. These measurements validated that the ROIC is ready for 3D integration into a PDC for systems in medical imaging, particle physics, and quantum sciences.
