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arXiv 1302.7007cs.ET
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纳米级忆阻器突触在类脑计算架构中的集成

Integration of nanoscale memristor synapses in neuromorphic computing architectures

Giacomo Indiveri, Bernabe Linares-Barranco, Robert Legenstein, George Deligeorgis, Themistoklis Prodromakis

摘要:

传统的神经计算架构和人工神经网络通常是在与神经科学没有或松散联系的情况下开发的。因此,他们在很大程度上忽略了生物神经处理系统的关键特征,例如它们的极低功耗特征或它们使用有限精度、高度可变和不可靠组件的大规模并行阵列进行鲁棒和高效计算的能力。纳米技术的最新发展使得非常紧凑和低功耗,但也可变和不可靠的固态器件,可以潜在地扩展利用CMOS技术的产品。特别是,忆阻器被认为是一种有前途的解决方案,用于模拟生物突触的关键特征,因为它们的纳米尺寸,它们能够存储每个元素的多位信息,以及写入不同状态所需的低能量。在本文中,我们首先回顾了神经和神经形态计算方法,可以最好地利用忆阻器和规模设备的属性,然后提出了一种新的混合忆阻器CMOS神经形态电路,它代表了从传统的神经计算方法的根本出发,因为它使用忆阻器直接模拟真实突触的生物物理和时间动态。我们指出忆阻器在传统的神经计算架构和提出的混合忆阻器-CMOS电路的使用之间的差异,并认为这种电路是如何实现大脑启发的概率计算范例,是强大的可变性和容错设计的理想积木。

英文摘要:

Conventional neuro-computing architectures and artificial neural networks have often been developed with no or loose connections to neuroscience. As a consequence, they have largely ignored key features of biological neural processing systems, such as their extremely low-power consumption features or their ability to carry out robust and efficient computation using massively parallel arrays of limited precision, highly variable, and unreliable components. Recent developments in nano-technologies are making available extremely compact and low-power, but also variable and unreliable solid-state devices that can potentially extend the offerings of availing CMOS technologies. In particular, memristors are regarded as a promising solution for modeling key features of biological synapses due to their nanoscale dimensions, their capacity to store multiple bits of information per element and the low energy required to write distinct states. In this paper, we first review the neuro- and neuromorphic-computing approaches that can best exploit the properties of memristor and-scale devices, and then propose a novel hybrid memristor-CMOS neuromorphic circuit which represents a radical departure from conventional neuro-computing approaches, as it uses memristors to directly emulate the biophysics and temporal dynamics of real synapses. We point out the differences between the use of memristors in conventional neuro-computing architectures and the hybrid memristor-CMOS circuit proposed, and argue how this circuit represents an ideal building block for implementing brain-inspired probabilistic computing paradigms that are robust to variability and fault-tolerant by design.

机构、总结、中文摘要均由AI分析而来,可能存在错误,请以论文正文为准。

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