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BrainScaleS 晶圆级神经形态系统的突触损失估计

Synapse Loss Estimation for the BrainScaleS Wafer-scale Neuromorphic System

Bernhard Vogginger, Christian Mayr

arXiv 2610.07321首次发表:更新:

发表机构

TUD Dresden University of Technology(德累斯顿工业大学)

机构由 AI 辅助整理,请以论文原文为准。

AI 中文总结

本文针对BrainScaleS晶圆级神经形态系统,提出基于概率分布和路由架构的突触损失估计方法,预测映射均匀随机网络时的损失,并验证其能力与局限,助力映射优化与硬件设计。

AI 中文摘要

神经形态硬件将记忆(突触)和计算(神经元)集成到同一硅基板上,以规避冯·诺依曼瓶颈。通过这种方式,神经形态计算旨在使计算神经科学模拟和人工智能处理更快、更节能。常见的交叉阵列架构将突触矩阵(模拟、混合信号或数字)与神经元阵列集成到神经突触核心中,而多个核心通过专用的脉冲路由网络互连。BrainScaleS 晶圆级系统就是这类神经形态架构之一,它通过高度可配置的神经突触核心支持密集和稀疏连接,从而实现非常灵活的网络架构。然而,当计算神经科学的网络模型映射到 BrainScaleS 晶圆时,可能会发生突触损失,这意味着由于硬件的受限连接,某些模型突触没有可用的硬件突触。在本工作中,我们从理论和经验上分析了将均匀随机网络映射到 BrainScaleS 时的突触损失。我们首先基于概率分布和硬件的突触路由架构,开发了一种估计无突触损失的最大规模网络的方法。接下来,我们采用该方法预测更密集或更大网络模型的突触损失。然后,我们将预测结果与实际运行的映射软件结果进行比较:结果显示了 BrainScaleS 系统本身的能力和局限性,并指出了当前映射算法的不足。所开发的方法在多个方面具有帮助:在为给定网络模型映射到 BrainScaleS 时找到最优设置,作为映射软件的基准,以及作为新硬件设计空间探索的工具。

英文摘要

Neuromorphic hardware combines memory (synapses) and computation (neurons) into the same silicon substrate to avoid the von-Neumann bottleneck. This way, neuromorphic computing aims to make computational neuroscience simulations and AI processing faster and more energy-efficient. The common crossbar architecture integrates a synapse matrix (analog, mixed-signal or digital) with a neuron array into a neurosynaptic core, whereas multiple cores are interconnected via a dedicated spike routing network. One of such neuromorphic architecture is the BrainScaleS wafer-scale system which allows the realization of very flexible network architecture, supporting both dense and sparse connectivity by highly configurable neurosynaptic cores. Yet, when network models from computational neuroscience are mapped to the BrainScaleS wafer, synapse loss can occur which means that for some model synapses no hardware synapse is available due to the restricted connectivity of the hardware. In this work we analyze the synapse loss when mapping uniform random networks to BrainScaleS both theoretically and empirically. We first develop a methodology to estimate maximum-sized networks without synapse loss based on probability distributions and the hardware's synapse routing architecture. Next, we adopt the methodology to predict the synapse loss for denser or larger network models. Then, we compare the predictions with results from actual runs of the mapping software: The results show the capabilities and limitations of the BrainScaleS system itself and spot shortcomings of the current mapping algorithms. The developed methodology can be helpful in multiple ways: to find the optimal settings when mapping a given network model to BrainScaleS, to act as a benchmark for the mapping software, and as tool for design space exploration for new hardware.

Comments27 pages, 14 figures, version 1 using MappingTool

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