The saturation-based reasoning methods are among the most theoretically developed ones and are used by most of the state-of-the-art first-order logic reasoners. In the last decade there was a sharp increase in performance of such systems, which I attribute to the use of advanced calculi and the intensified research in implementation techniques. However, nowadays we are witnessing a slowdown in performance progress, which may be considered as a sign that the saturation-based technology is reaching its inherent limits. The position I am trying to put forward in this paper is that such scepticism is premature and a sharp improvement in performance may potentially be reached by adopting new architectural principles for saturation. The top-level algorithms and corresponding designs used in the state-of-the-art saturation-based theorem provers have (at least) two inherent drawbacks: the insufficient flexibility of the used inference selection mechanisms and the lack of means for intelligent prioritising of search directions. In this position paper I analyse these drawbacks and present two ideas on how they could be overcome. In particular, I propose a flexible low-cost high-precision mechanism for inference selection, intended to overcome problems associated with the currently used instances of clause selection-based procedures. I also outline a method for intelligent prioritising of search directions, based on probing the search space by exploring generalised search directions. I discuss some technical issues related to implementation of the proposed architectural principles and outline possible solutions.
A Novel Approach to Balance Convenience and Nutrition in Meals With Long-Term Group Recommendations and Reasoning on Multimodal Recipes and its Implementation in BEACON
A VLSI Design and Implementation for a Real-Time Approximate Reasoning
Rockwell International Science Center（罗克韦尔国际科学中心）
在基于规则的专家系统中，不确定性推理的作用变得越来越重要，因为人类专家给出的知识通常是不确定的或不精确的。我们已经成功地设计了一个超大规模集成电路芯片，它可以执行一个完整的推理过程的基础上模糊逻辑。VLSI模糊推理机的设计强调简单性、可扩展性和效率（运算速度和布局面积）。它采用2.5 um CMOS工艺制造。推理机由三个主要部分组成：规则集存储器、推理处理器和控制器。在该实现中，规则集存储器由只读存储器（ROM）实现。控制器由两个计数器组成。在推理处理器中，每个规则都有一条数据路径。推理规则的数量可以增加，从而向推理处理器添加更多的数据路径。所有规则都是并行执行的，但每个规则都是串行处理的。本文提出的模糊推理的逻辑结构很好地映射到VLSI结构上。使用两相非重叠时钟方案。时序测试表明，推理机可以工作在约20.8 MHz。这转化为每秒大约80，000个模糊逻辑推理（FLIPS）的执行速度，并且表明推理引擎适合于要求实时的【形】应用。潜在的应用包括智能机器人系统的指挥和控制、过程控制、导弹和飞机制导以及其他高性能机器的决策。
