高级综合中提高电路性能的行为变换
Behavioural Transformation to Improve Circuit Performance in High-Level Synthesis
摘要：
早期的调度算法通常将时钟周期的持续时间调整为最慢操作的执行时间。这导致在执行更快操作的周期中浪费了大量的松弛时间。为了减少浪费的时间，已经采用了多周期和链接技术。虽然这些技术已经产生了成功的设计，但其有效性往往是有限的，由于面积增量，可能来自链接，和额外的疲劳，可能来自多循环。在本文中，我们提出了一种优化方法，解决了时间约束的调度问题，通过将行为规范转化为新的，其随后的合成大大提高了电路性能。我们的建议打破了一些规范的操作，允许他们在几个可能不连续的周期执行，也计算几个数据相关的操作片段在同一个周期。为此，它考虑了电路延迟和每个规范操作的执行时间。进行的实验结果表明，从优化规格得到的电路平均60%的速度比从原始规格合成的，只有轻微的增量，在电路面积。
英文摘要：
Early scheduling algorithms usually adjusted the clock cycle duration to the execution time of the slowest operation. This resulted in large slack times wasted in those cycles executing faster operations. To reduce the wasted times multi-cycle and chaining techniques have been employed. While these techniques have produced successful designs, its effectiveness is often limited due to the area increment that may derive from chaining, and the extra latencies that may derive from multicycling. In this paper we present an optimization method that solves the time-constrained scheduling problem by transforming behavioural specifications into new ones whose subsequent synthesis substantially improves circuit performance. Our proposal breaks up some of the specification operations, allowing their execution during several possibly unconsecutive cycles, and also the calculation of several data-dependent operation fragments in the same cycle. To do so, it takes into account the circuit latency and the execution time of every specification operation. The experimental results carried out show that circuits obtained from the optimized specification are on average 60% faster than those synthesized from the original specification, with only slight increments in the circuit area.
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
