发表机构
Indian Institute of Technology Bombay（印度理工学院孟买分校）
机构由 AI 辅助整理，请以论文原文为准。AI 中文总结
本文提出基于AHIR框架的异步电路高级综合ASIC设计流程，生成延迟不敏感控制器与捆绑数据路径，形式化时序约束并开发静态分析器，通过AES加密算法端到端实现验证正确性与性能。
AI 中文摘要
异步电路相对于其同步对应电路具有一些优势，例如更低的空闲功耗、潜在更低的延迟、不存在时钟分布问题等。然而，工业规模的电子设计自动化（EDA）支持，特别是针对从命令式程序进行异步系统高级综合（HLS）的支持，仍然有限。我们提出了一种使用AHIR高级综合框架从命令式程序综合异步电路的方法。该框架以受限形式的Petri网形式对控制路径进行建模，这些Petri网在构造上是1-安全的且活的。在这项工作中，我们从AHIR中的这种表示开始，生成具有延迟不敏感控制器、单轨数据路径以及控制器与数据路径之间类似于微流水线架构的捆绑数据交互的异步电路。我们形式化了生成电路正确运行所需的时序约束，并表明这些约束是单侧的（可行的）、必要且充分的。我们还开发了一个静态时序分析器来检查电路是否满足这些约束。我们的流程与现成的ASIC工具链和标准同步单元库无缝集成。为了演示我们的方法，我们展示了一个AES加密算法的端到端实现，并使用布局后电路仿真来验证正确性并评估所得电路的性能。
英文摘要
Asynchronous circuits have some benefits over their synchronous counterparts, such as lower idle power consumption, potentially lower latency, absence of clock distribution issues, among others. However, industry-scale electronic design automation (EDA) support, particularly for high-level synthesis (HLS) of asynchronous systems from imperative programs, remains limited. We present an approach to synthesize asynchronous circuits from imperative programs using the AHIR HLS framework. The framework models the control path in the form of a restricted form of Petri nets that are 1-safe and live by construction. In this work, we start with this representation in AHIR and generate asynchronous circuits with a delay insensitive controller, a single-rail data path with bundled-data interaction between the controller and the data path that resembles the micropipelines architecture. We formalize the timing constraints required for correct functioning of the generated circuit and show that those constraints are one sided (feasible), necessary and sufficient. We have also developed a static timing analyzer to check that the circuit meets these constraints. Our flow integrates seamlessly with off-the-shelf ASIC toolchains and standard synchronous cell libraries. To demonstrate our approach, we show an end to end implementation of an AES encryption algorithm and use post layout circuit simulation to verify the correctness and estimate the performance of the resultant circuit.
Comments20 pages, 23 figures
