差分逻辑电路的恒功耗设计方法
Design Method for Constant Power Consumption of Differential Logic Circuits
摘要：
侧信道攻击是灵巧卡和其他嵌入式设备的主要安全问题。他们分析功耗的变化，以找到在安全IC内实现的加密算法的秘密密钥。为了解决这个问题，在安全IC中使用具有独立于输入信号的恒定功耗的逻辑门。本文提出了一种全连接差分下拉网络的设计方法。全连接差分下拉网络是晶体管网络，对于任何互补输入组合，其将网络的所有内部节点连接到网络的外部节点之一。它们是无记忆的，因此具有恒定的负载电容和功耗。这种类型的网络用于专用逻辑门，以保证内部节点对逻辑门总功耗的贡献恒定。
英文摘要：
Side channel attacks are a major security concern for smart cards and other embedded devices. They analyze the variations on the power consumption to find the secret key of the encryption algorithm implemented within the security IC. To address this issue, logic gates that have a constant power dissipation independent of the input signals, are used in security ICs. This paper presents a design methodology to create fully connected differential pull down networks. Fully connected differential pull down networks are transistor networks that for any complementary input combination connect all the internal nodes of the network to one of the external nodes of the network. They are memoryless and for that reason have a constant load capacitance and power consumption. This type of networks is used in specialized logic gates to guarantee a constant contribution of the internal nodes into the total power consumption of the logic gate.
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
