亚100纳米工艺中提高成品率的流水线延迟统计建模与工艺变化下的流水线设计
Statistical Modeling of Pipeline Delay and Design of Pipeline under Process Variation to Enhance Yield in sub-100nm Technologies
摘要：
流水线电路的工作频率由最慢流水线级的延迟决定。然而，在亚100纳米技术体系中的统计延迟变化下，最慢的阶段不容易识别，并且相对于目标延迟的流水线产率的估计是一个具有挑战性的问题。我们已经提出了分析模型来估计产量的流水线设计的基础上延迟分布的各个管道阶段。使用所提出的模型，我们已经表明，逻辑深度的变化和阶段延迟之间的不平衡可以提高流水线的产量。为了提高成品率，提出了一种基于统计的流水线电路优化设计方法。优化结果表明，在相同的面积和性能下，与平衡设计相比，适当的级间延迟不平衡可使设计成品率提高9%（在成品率约束下，面积减少约8.4%）。
英文摘要：
Operating frequency of a pipelined circuit is determined by the delay of the slowest pipeline stage. However, under statistical delay variation in sub-100nm technology regime, the slowest stage is not readily identifiable and the estimation of the pipeline yield with respect to a target delay is a challenging problem. We have proposed analytical models to estimate yield for a pipelined design based on delay distributions of individual pipe stages. Using the proposed models, we have shown that change in logic depth and imbalance between the stage delays can improve the yield of a pipeline. A statistical methodology has been developed to optimally design a pipeline circuit for enhancing yield. Optimization results show that, proper imbalance among the stage delays in a pipeline improves design yield by 9% for the same area and performance (and area reduction by about 8.4% under a yield constraint) over a balanced design.
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