FPGA Co-processor for the ALICE High Level Trigger
G. Grastveit, H. Helstrup, V. Lindenstruth, C. Loizides, D. Roehrich, B. Skaali, T. Steinbeck, R. Stock, H. Tilsner, K. Ullaland, A. Vestbo, T. Vik
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Talk from the 2003 Computing in High Energy and Nuclear Physics (CHEP03), La Jolla, Ca, USA, March 2003, 5 pages, LaTeX, 8 eps figures. PSN THHT001, eConf C030324
The High Level Trigger (HLT) of the ALICE experiment requires massive parallel computing. One of the main tasks of the HLT system is two-dimensional cluster finding on raw data of the Time Projection Chamber (TPC), which is the main data source of ALICE. To reduce the number of computing nodes needed in the HLT farm, FPGAs, which are an intrinsic part of the system, will be utilized for this task. VHDL code implementing the Fast Cluster Finder algorithm, has been written, a testbed for functional verification of the code has been developed, and the code has been synthesized
An experimental digital correlated double sampler (DCDS) video processor has been implemented in a Xilinx Artix FPGA. It uses an Opal Kelly XEM7010-A50 module that comes with an integrated USB2 interface for easy interfac-ing to a data acquisition PC. The FPGA has been coupled to a dual 16-bit 20Msps ADC and video preamplifiers. A synthetic CCD video waveform was provided by a high speed DAC also under FPGA control. VHDL-defined hardware implemented the differential averager algorithm which has been shown to give the optimal signal to noise ratio over a wide range of readout speeds. Hardware d…
The COMET experiment at J-PARC aims to search for the neutrinoless transition of a muon to an electron. We have developed the readout electronics board called ROESTI for the COMET straw tube tracker. We plan to install the ROESTI in the gas manifold of the detector. The number of vacuum feedthroughs needs to be reduced due to space constraints and cost limitations. In order to decrease the number of vacuum feedthroughs drastically, we developed a network processor with a daisy-chain function of Gigabit Ethernet for the FPGA on the ROESTI. We implemented two SiTCPs, which are hardware-based TCP…
Electronic systems for qubit control and measurement serve as a bridge between quantum programming language and quantum information processors. With the rapid development of superconducting quantum circuit (SQC) technology, synchronization in a large-scale system, low-latency execution, and low noise are required for electronic systems. Here, we present a field-programmable gate array (FPGA)-based electronic system with a distributed synchronous clock and trigger architecture. The system supports synchronous control of qubits with jitters of approximately 5 ps. We implement a real-time digital…
A Large Ion Collider Experiment (ALICE) is one of the four major experiments conducted at the CERN Large Hadron Collider (LHC). The ALICE detector is currently undergoing an upgrade for the upcoming Run 3 at the LHC. The new Inner Tracking System (ITS) sub-detector is part of this upgrade. The front-end electronics of the ITS is composed by 192 Readout Units, installed in a radiation environment. Single Event Upsets (SEUs) in the SRAM-based Xilinx Kintex Ultrascale FPGAs used in the ITS readout represent a real concern. To clear SEUs affecting the Kintex configuration memory, a secondary Flash…
At the Large Hadron Collider at CERN in Geneva, Switzerland, atomic nuclei are collided at ultra-relativistic energies. Many final-state particles are produced in each collision and their properties are measured by the ALICE detector. The detector signals induced by the produced particles are digitized leading to data rates that are in excess of 48 GB/$s$. The ALICE High Level Trigger (HLT) system pioneered the use of FPGA- and GPU-based algorithms to reconstruct charged-particle trajectories and reduce the data size in real time. The results of the reconstruction of the collision events, avai…
The ALICE experiment at the LHC is equipped with an electromagnetic calorimeter (EMCal) designed to enhance its capabilities for jet measurement. In addition, the EMCal enables triggering on high energy jets. Based on the previous development made for the Photon Spectrometer (PHOS) level-0 trigger, a specific electronic upgrade was designed in order to allow fast triggering on high energy jets (level-1). This development was made possible by using the latest generation of FPGAs which can deal with the instantaneous incoming data rate of 26 Gbit/s and process it in less than 4 μs.
The ALICE (A Large Ion Collider Experiment) experiment focuses on the study of the quark-gluon plasma as a product of heavy-ion collisions at the CERN LHC (Large Hadron Collider). During the Long Shutdown 2 of the LHC in 2019-2020, a major upgrade is underway in order to cope with a hundredfold input data rate increase with peaks of up to 3.4 TB/s. This upgrade includes the new Online-Offline computing system called O2. The O2 readout chain runs on commodity Linux servers equipped with custom PCIe FPGA-based readout cards; the PCIe v3 x16, Intel Arria 10-based CRU (Common Readout Unit) and the…
A new Muon-to-Central-Trigger Processor Interface (MUCTPI) was built as part of the upgrade of the ATLAS Level-1 trigger system for the next Run of the Large Hadron Collider at CERN. The MUCTPI has 208 high-speed optical serial links for receiving muon candidates from the muon trigger detectors. Three high-end FPGAs are used for real-time processing of the muon candidates, for sending trigger information to other parts of the trigger system, and for sending summary information to the data acquisition and monitoring system. A System-on-Chip (SoC) is used for the control, configuration and monit…
We are developing a new readout board with a newer generation field-programmable gate array (FPGA) and the 10-gigabit ethernet to improve the performance and usability of the current readout board based on the 1-gigabit Ethernet. In this new readout board, the SiTCP-XG network processor supporting 10-gigabit Ethernet was implemented. SiTCP is a network processor circuit running on FPGA, and SiTCP-XG is the newly developed version of the SiTCP that supports 10-gigabit Ethernet. Before developing the new board, we constructed a prototype system using the Xilinx FPGA evaluation board KC705 to eva…
We present results of an R&D study for a specialized processor capable of precisely reconstructing, in pixel detectors, hundreds of charged-particle tracks from high-energy collisions at 40 MHz rate. We apply a highly parallel pattern-recognition algorithm, inspired by studies of the processing of visual images by the brain as it happens in nature, and describe in detail an efficient hardware implementation in high-speed, high-bandwidth FPGA devices. This is the first detailed demonstration of reconstruction of offline-quality tracks at 40 MHz and makes the device suitable for processing Large…
The ALICE Central Trigger Processor (CTP) is going to be upgraded for LHC Run 3 with completely new hardware and a new Trigger and Timing Control (TTC-PON) system based on a Passive Optical Network (PON) system. The new trigger system has been designed as dead time free and able to transmit trigger data at 9.6 Gbps. A new universal trigger board has been designed, where by changing the FMC card, it can function as a CTP or as a LTU. It is based on the Xilinx Kintex Ultrascale FPGA and upgraded TTC-PON. The new trigger system and the prototype of the trigger board will be presented.
A Large Ion Collider Experiment (ALICE) at the Large Hadron Collider (LHC) at CERN went through a major upgrade in which some of its subdetectors were replaced with new ones, while others are equipped with new electronics. The aim of the upgrade is to withstand higher collision rates during the third running period (Run 3), which started in 2022. As part of the upgrade, certain subdetectors such as the Muon Trigger, renamed to Muon Identifier, now operate in a continuous, triggerless readout mode, in addition to the previous triggered readout mode. Due to the increased quantity of data, typica…
In Run-3, beginning in 2022, the LHCb software trigger will start reconstructing events at the LHC average crossing rate of 30 MHz. Within the upgraded DAQ system, LHCb established a testbed for new heterogeneous computing solutions for real-time event reconstruction, in view of future runs at even higher luminosities. One such solution is a highly-parallelized custom tracking processor ("Artificial Retina"), implemented in state of the art FPGA devices connected by fast serial links. We describe the status of a realistic prototype for the reconstruction of pixel tracking detectors that will r…
The Large Hadron Collider (LHC) at CERN is undergoing a major upgrade with the goal of increasing the luminosity as more statistics are needed for precision measurements. The presented work pertains to the corresponding upgrade of the ALICE Muon Trigger (MTR) Detector, now named the Muon Identifier (MID). Previously operated in a triggered readout manner, this detector has transitioned to continuous readout with time-delimited data payloads. However, this results in data rates much higher than the previous operation and hence a new Online-Offline (O2) computing system is also being developed f…
This paper reports on the development of a resource-efficient FPGA-based neural network regression model for potential applications in the future hardware muon trigger system of the ATLAS experiment at the Large Hadron Collider (LHC). Effective real-time selection of muon candidates is the cornerstone of the ATLAS physics programme. With the planned ATLAS upgrades for the High Luminosity LHC, an entirely new FPGA-based hardware muon trigger system will be installed that will process full muon detector data within a 10 $μs$ latency window. The large FPGA devices planned for this upgrade should …
