用于脉冲加速器的抗噪流实时数据采集结构
Noise-Tolerant Streaming Real-Time Data Acquisition Fabric for Pulsed Accelerators
摘要：
已经开发了一种噪声容忍数据通信结构，以满足下一代脉冲加速器（例如Next Linear Collider（“NLC”））处的快速反馈回路、机器保护系统、脉冲到脉冲排序和机器实验通信的实时数据采集和控制要求。该结构由“平台”或“片上系统”现场可编程门阵列（“FPGA”）构成，该FPGA包含嵌入式处理器、块存储器和经由用于标准网络（诸如千兆以太网）的点对点光纤物理链路的阵列互连的多千兆串行收发器。基于FPGA的链路硬件将不同优先级的消息分段为连续的固定长度数据信元序列，用包含较高优先级业务的消息中断较低优先级消息的信元流。通过将每个单元的几乎一半的内容专用于Reed-Solomon前向纠错码（“ECC”）数据来提供高水平的噪声容限。进一步的可靠性是通过硬件实现的算法，逐个细胞的接收确认，接收超时和可调的往返传播延迟后的重传，并为每个优先级单独的背压流量控制。
英文摘要：
A noise-tolerant data communications fabric has been developed to meet the real-time data acquisition and control requirements of fast feedback loops, machine protection systems, pulse-to-pulse sequencing, and machine-experiment communications at next-generation pulsed accelerators such as the Next Linear Collider ("NLC"). The fabric is constructed from "platform" or "system-on-a-chip" field programmable gate arrays ("FPGAs") containing embedded processors, block memory, and multi-gigabit serial transceivers interconnected via an array of point-to-point fiber-optic physical links for standard networks such as gigabit Ethernet. The FPGA-based link hardware segments messages of varying priorities into a continuous sequence of fixed-length data cells, interrupting the cell stream of lower priority messages with those comprising higher priority traffic. A high level of noise-tolerance is provided by dedicating almost half the contents of each cell to Reed-Solomon forward error correcting code ("ECC") data. Further reliability is achieved by hardware implementation of algorithms for cell-by-cell receipt acknowledgment, receipt timeout and retransmission after a tunable round-trip propagation delay, and separate backpressure flow control for each priority.
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
