Most input buffered packet switches internally segment variable-length packets into fixed-length cells. The last cell in a segmented packet will contain overhead bytes if the packet length is not evenly divisible by the cell length. Switch speed-up is used to compensate for this overhead. In this paper, we develop an analytical model of a single-server queue where an input stream of packets is segmented into cells for service. Analytical models are developed for M/M/1, M/H2/1, and M/E2/1 queues with a discretized (or quantized) service time. These models and simulation using real packet traces are used to evaluate the effect of speed-up on mean queue length. We propose and evaluate a new method of segmenting a packet trailer and subsequent packet header into a single cell. This cell merging method reduces the required speed-up. No changes to switch-matrix scheduling algorithms are needed. Simulation with a packet trace shows a reduction in the needed speed-up for an iSLIP scheduled input buffered switch.
Given the rapid increase in traffic, greater demands have been put on high-speed switching systems. Such systems have to simultaneously meet several constraints, e.g., high throughput, low delay and low complexity. This makes it challenging to design an efficient scheduling algorithm, and has consequently drawn considerable research interest. However, previous results either cannot provide a $100\%$ throughput guarantee without a speedup, or require a complex centralized scheduler. In this paper, we design a {\it distributed} $100 \%$ throughput algorithm for crosspoint buffered switches, call…
In this paper, we propose a cognitive protocol that involves cooperation between the primary and secondary users. In addition to its own queue, the secondary user (SU) has a queue to store, and then relay, the undelivered primary packets. When the primary queue is nonempty, the SU remains idle and attempts to decode the primary packet. When the primary queue is empty, the SU splits the total channel bandwidth into two orthogonal subbands and assigns each to a queue probabilistically. We show the advantage of the proposed protocol over the prioritized cognitive relaying (PCR) protocol in which …
This paper studies the buffered Aloha with K-exponential backoff collision resolution algorithms. The buffered Aloha network is modeled as a multi-queue single-server system. We adopt a widely used approach in packet switching systems to decompose the multi-queue system into independent first-in-first-out (FIFO) queues, which are hinged together by the probability of success of head-of-line (HOL) packets. A unified method is devised to tackle the stability and throughput problems of K-exponential backoff with any cutoff phase K. For networks with a finite number of nodes, we show that the K-ex…
This two-part paper series studies the performance of buffered Aloha networks with K-Exponential Backoff collision resolution algorithms. Part I focuses on stability and throughput analysis and Part II presents the delay analysis. In Part I, the buffered Aloha network is modeled as a multi-queue single-server system. We adopt a widely used approach in packet switching systems to decompose the multi-queue system into independent first-in-first-out (FIFO) queues, which are hinged together by the probability of success of head-of-line (HOL) packets. A unified method is devised to tackle the stabi…
Input buffered switches with Virtual Output Queueing (VOQ) can be unstable when presented with unbalanced loads. Existing scheduling algorithms, including iSLIP for Input Queued (IQ) switches and Round Robin (RR) for Combined Input and Crossbar Queued (CICQ) switches, exhibit instability for some schedulable loads. We investigate the use of a queue length threshold and bursting mechanism to achieve stability without requiring internal speed-up. An analytical model is developed to prove that the burst stabilization protocol achieves stability and to predict the minimum burst value needed as a f…
In Software Defined Networks, where the network control plane can be programmed by updating switch rules, consistently updating switches is a challenging problem. In a per-packet consistent update (PPC), a packet either matches the new rules added or the old rules to be deleted, throughout the network, but not a combination of both. PPC must be preserved during an update to prevent packet drops and loops, provide waypoint invariance and to apply policies consistently. No algorithm exists today that confines changes required during an update to only the affected switches, yet preserves PPC and …
Strict-Priority Packet Delay in Switches with Transmit-Ring Buffering
Technical University of Munich（慕尼黑工业大学）；Chair of Communication Networks at the Technical University of Munich（慕尼黑工业大学通信网络讲席）；University of Klagenfurt（克拉根福大学）；Department of Statistics, University of Klagenfurt（克拉根福大学统计系）
Compared to fixed-function switches, the flexibility of programmable switches comes at a cost, as programmer mistakes frequently result in subtle bugs in the network data plane. In this paper, we present the design and implementation of FP4, a fuzz-testing framework for P4 switches that achieves high expressiveness, coverage, and scalability. FP4 directly tests running switches by generating semi-random input packets and observing their resulting execution in the data plane. To achieve high coverage and scalability, at runtime, FP4 leverages P4 itself with another "tester" switch that generate…
We propose a configuration scheme for a load-balancing Clos-network packet switch that has split central modules and buffers in between the split modules. Our split-central-buffered Load-Balancing Clos-network (LBC) switch is cell based. The switch has four stages, namely input, central-input, central-output, and output stages. The proposed configuration scheme uses a pre-determined and periodic interconnection pattern in the input and split central modules to load-balance and route traffic. The LBC switch has low configuration complexity. The operation of the switch includes a mechanism appli…
Many algorithms for congestion control, scheduling, network measurement, active queue management, security, and load balancing require custom processing of packets as they traverse the data plane of a network switch. To run at line rate, these data-plane algorithms must be in hardware. With today's switch hardware, algorithms cannot be changed, nor new algorithms installed, after a switch has been built. This paper shows how to program data-plane algorithms in a high-level language and compile those programs into low-level microcode that can run on emerging programmable line-rate switching chi…
As one of the most popular south-bound protocol of software-defined networking(SDN), OpenFlow decouples the network control from forwarding devices. It offers flexible and scalable functionality for networks. These advantages may cause performance issues since there are performance penalties in terms of packet processing speed. It is important to understand the performance of OpenFlow switches and controllers for its deployments. In this paper we model the packet processing time of OpenFlow switches and controllers. We mainly analyze how the probability of packet-in messages impacts the perfor…
Network switches and routers need to serve packet writes and reads at rates that challenge the most advanced memory technologies. As a result, scaling the switching rates is commonly done by parallelizing the packet I/Os using multiple memory units. For improved read rates, packets can be coded upon write, thus giving more flexibility at read time to achieve higher utilization of the memory units. This paper presents a detailed study of coded network switches, and in particular how to design them to maximize the throughput advantages over standard uncoded switches. Toward that objective the pa…
The growing trends of data centers over last decades including social networking, cloud-based applications and storage technologies enabled many advances to take place in the networking area. Recent changes imply continuous demand for bandwidth to manage the large amount of packetized traffic. Cluster switches and routers make the switching fabric in a Data Center Network (DCN) environment and provide interconnectivity between elements of the same DC and inter DCs. To handle the constantly variable loads, switches need deliver outstanding throughput along with resiliency and scalability for DC…
Flow scheduling is crucial in data centers, as it directly influences user experience of applications. According to different assumptions and design goals, there are four typical flow scheduling problems/solutions: SRPT, LAS, Fair Queueing, and Deadline-Aware scheduling. When implementing these solutions in commodity switches with limited number of queues, they need to set static parameters by measuring traffic in advance, while optimal parameters vary across time and space. This paper proposes a generic framework, namely QCluster, to adapt all scheduling problems for limited number of queues.…
High Speed Downlink Packet Access (HSDPA) was introduced to UMTS radio access segment to provide higher capacity for new packet switched services. As a result, packet switched sessions with multiple diverse traffic flows such as concurrent voice and data, or video and data being transmitted to the same user are a likely commonplace cellular packet data scenario. In HSDPA, Radio Access Network (RAN) buffer management schemes are essential to support the end-to-end QoS of such sessions. Hence in this paper we present the end-to-end performance study of a proposed RAN buffer management scheme for…
Traditionally, the data plane has been designed with fixed functions to forward packets using a small set of protocols. This closed-design paradigm has limited the capability of the switches to proprietary implementations which are hardcoded by vendors, inducing a lengthy, costly, and inflexible process. Recently, data plane programmability has attracted significant attention from both the research community and the industry, permitting operators and programmers in general to run customized packet processing function. This open-design paradigm is paving the way for an unprecedented wave of inn…
Packet trimming is a primitive that has been proposed for datacenter networks: to minimize latency, switches run small queues; when the queue overflows, rather than dropping packets the switch trims off the packet payload and either forwards the header to the destination or back to the source. In this way a low latency network that is largely lossless for metadata can be built. Ideally, trimming would be implemented as a primitive in switch ASICs, but hardware development cycles are slow, costly, and require demonstrated customer demand. In this paper we investigate how trimming can be impleme…
Internet traffic continues to grow exponentially, calling for switches that can scale well in both size and speed. While load-balanced switches can achieve such scalability, they suffer from a fundamental packet reordering problem. Existing proposals either suffer from poor worst-case packet delays or require sophisticated matching mechanisms. In this paper, we propose a new family of stable load-balanced switches called "Sprinklers" that has comparable implementation cost and performance as the baseline load-balanced switch, but yet can guarantee packet ordering. The main idea is to force all…
Benes networks are constructed with simple switch modules and have many advantages, including small latency and requiring only an almost linear number of switch modules. As circuit-switches, Benes networks are rearrangeably non-blocking, which implies that they are full-throughput as packet switches, with suitable routing. Routing in Benes networks can be done by time-sharing permutations. However, this approach requires centralized control of the switch modules and statistical knowledge of the traffic arrivals. We propose a backpressure-based routing scheme for Benes networks, combined with e…
Network performance problems are notoriously difficult to diagnose. Prior profiling systems collect performance statistics by keeping information about each network flow, but maintaining per-flow state is not scalable on resource-constrained NIC and switch hardware. Instead, we propose sketch-based performance monitoring using memory that is sublinear in the number of flows. Existing sketches estimate flow monitoring metrics based on flow sizes. In contrast, performance monitoring typically requires combining information across pairs of packets, such as matching a data packet with its acknowle…
By extending the traditional store-and-forward mechanism, network coding has the capability to improve a network's throughput, robustness, and security. Given the fundamentally different packet processing required by this new paradigm and the inflexibility of hardware, existing solutions are based on software. As a result, they have limited performance and scalability, creating a barrier to its wide-spread adoption. By leveraging the recent advances in programmable networking hardware, in this paper we propose a random linear network coding data plane written in P4, as a first step towards a p…
Software-defined networking (SDN) allows operators to control the behavior of a network by programatically managing the forwarding rules installed on switches. However, as is common in distributed systems, it can be difficult to ensure that certain consistency properties are preserved during periods of reconfiguration. The widely-accepted notion of PER-PACKET CONSISTENCY requires every packet to be forwarded using the new configuration or the old configuration, but not a mixture of the two. If switches can be updated in some (partial) order which guarantees that per-packet consistency is prese…
Hybrid circuit and packet switching for data center networking (DCN) has received considerable research attention recently. A hybrid-switched DCN employs a much faster circuit switch that is reconfigurable with a nontrivial cost, and a much slower packet switch that is reconfigurable with no cost, to interconnect its racks of servers. The research problem is, given a traffic demand matrix (between the racks), how to compute a good circuit switch configuration schedule so that the vast majority of the traffic demand is removed by the circuit switch, leaving a remaining demand matrix that contai…
We propose a three-stage load balancing packet switch and its configuration scheme. The input- and central-stage switches are bufferless crossbars, and the output-stage switches are buffered crossbars. We call this switch ThRee-stage Clos-network swItch with queues at the middle stage and DEtermiNisTic scheduling (TRIDENT), and the switch is cell based. The proposed configuration scheme uses predetermined and periodic interconnection patterns in the input and central modules to load-balance and route traffic, therefore; it has low configuration complexity. The operation of the switch includes …
This report deals with the design of handover schemes for radio access networks (RAN) in 5G networks, using programmable data plane switches. In 5G networks, the NG-RAN architecture splits the Base Band Unit (BBU) into Central and Distributed Units (CU and DU). This structure has created a mid-haul Network, connecting CUs and DUs. The recent advancements in dataplane programmability can be used to enhance system performance. We show how P4 switches can be used to parse the packets between DU, CU, and Back Haul (Core Network) for potential system improvements. In particular, we consider the sce…
Traditional IP multicast routing is not suitable for cloud data center (DC) networks due to the need for supporting large numbers of groups with large group sizes. State-of-the-art DC multicast routing approaches aim to overcome the scalability issues by, for instance, taking advantage of the symmetry of DC topologies and the programmability of DC switches to compactly encode multicast group information inside packets, thereby reducing the overhead resulting from the need to store the states of flows at the network switches. However, although these scale well with the number of multicast group…
This paper aims at contributing to the ongoing debate on how to bring programmability of stateful packet processing tasks inside the network switches, while retaining platform independency. Our proposed approach, named "Open Packet Processor" (OPP), shows the viability (via an hardware prototype relying on commodity HW technologies and operating in a strictly bounded number of clock cycles) of eXtended Finite State Machines (XFSM) as low-level data plane programming abstraction. With the help of examples, including a token bucket and a C4.5 traffic classifier based on a binary tree, we show th…
Modern switches have packet processing capacity of up to multi-tera bits per second, and they are also becoming more and more programmable. We seek to understand whether the programmability can translate packet processing capacity to computational power for parallel computing applications. In this paper, we first develop a simple mathematical model to understand the costs and overheads of data plane computation. Then we validate the the performance benefits of offloading computation to network. Using experiments on real data center network, we finnd that offloading computation to the data plan…
Network Function (NF) deployments suffer from poor link goodput, because popular NFs such as firewalls process only packet headers while receiving and transmitting complete packets. As a result, unnecessary packet payloads needlessly consume link bandwidth. We introduce PayloadPark, which improves goodput by temporarily parking packet payloads in the stateful memory of dataplane programmable switches. PayloadPark forwards only packet headers to NF servers, thereby saving bandwidth between the switch and the NF server. PayloadPark is a transparent in-network optimization that complements existi…
Traditionally, switches only provide forwarding services and have no credits on computation in distributed computing frameworks. The emerging programmable switches make in-network computing (INC) possible, i.e., offloading some computation to the switch data plane. While some proposals have attempted to offload computation onto special hardwares (e.g., NetFPGA), many practical issues have not been addressed. Therefore, we propose P4COM - a user-friendly, memory-efficient, and fault-tolerant framework realizing in-network computation (e.g., MapReduce) with programmable switches. P4COM consists …
Today, network devices share buffer across priority queues to avoid drops during transient congestion. While cost-effective most of the time, this sharing can cause undesired interference among seemingly independent traffic. As a result, low-priority traffic can cause increased packet loss to high-priority traffic. Similarly, long flows can prevent the buffer from absorbing incoming bursts even if they do not share the same queue. The cause of this perhaps unintuitive outcome is that today's buffer sharing techniques are unable to guarantee isolation across (priority) queues without statically…
Many recent papers have demonstrated fast in-network computation using programmable switches, running many orders of magnitude faster than CPUs. The main limitation of writing software for switches is the constrained programming model and limited state. In this paper we explore whether a new type of CPU, called the nanoPU, offers a useful middle ground, with a familiar C/C++ programming model, and potentially many terabits/second of packet processing on a single chip, with an RPC response time less than 1 $μ$s. To evaluate the nanoPU, we prototype and benchmark three common network services: p…
The possibility to offload, via a platform-agnostic specification, the execution of (some/part of the) control functions down to the switch and operate them at wire speed based on packet level events, would yield significant benefits in terms of control latency and reaction times, meanwhile retaining the SDN-type ability to program and instantiate a desired network operation from a central controller. While programmability inside the switches, at wire speed and using platform-independent abstractions, of "any possible'" control function seems well beyond the OpenFlow capabilities, in this pape…
Switches today provide a small set of scheduling algorithms. While we can tweak scheduling parameters, we cannot modify algorithmic logic, or add a completely new algorithm, after the switch has been designed. This paper presents a design for a programmable packet scheduler, which allows scheduling algorithms---potentially algorithms that are unknown today---to be programmed into a switch without requiring hardware redesign. Our design builds on the observation that scheduling algorithms make two decisions: in what order to schedule packets and when to schedule them. Further, in many schedulin…
This paper proposes an adaptive variant of Random Early Detection (RED) gateway queue management for packet-switched networks via a discrete state analog of the non-stationary Master Equation i.e. Markov process. The computation of average queue size, which appeared in the original RED algorithm, is altered by introducing a probability $P(l,t)$, which defines the probability of having $l$ number of packets in the queue at the given time $t$, and depends upon the previous state of the queue. This brings the advantage of eliminating a free parameter: queue weight, completely. Computation of tran…
This paper explores the application of a new algebraic method of edge coloring, called complex coloring, to the scheduling problems of input queued switches. The proposed distributed parallel scheduling algorithm possesses two important features: optimality and rearrangeability. Optimality ensures that the algorithm always returns a proper coloring with the minimum number of required colors, and rearrangeability allows partially re-coloring the existing connection patterns if the underlying graph only changes slightly. The running time of the proposed scheduling algorithm is on the order of $O…
We consider a new model for buffer management of network switches with Quality of Service (QoS) requirements. A stream of packets, each attributed with a value representing its Class of Service (CoS), arrives over time at a network switch and demands a further transmission. The switch is equipped with multiple queues of limited capacities, where each queue stores packets of one value only. The objective is to maximize the total value of the transmitted packets (i.e., the weighted throughput). We analyze a natural greedy algorithm, GREEDY, which sends in each time step a packet with the greates…
In a congested network link, synchronization effects between bandwidth-sharing TCP flows cause wide queue length oscillations, which may translate into poor link utilization if insufficiently buffered. We introduce global synchronization protection (GSP), a simple extension to the ordinary operation of a tail-drop queue that safely suppresses the flow synchronization. Our minimalistic solution is well suited for scaling with leading-edge link rates: it adds only few extra operations in the fast path and does not require accelerated memory access compared to the line rate. GSP makes it easier t…
Despite the high throughput and low complexity achieved by input scheduling based on Birkhoff-von-Neumann (BvN) decomposition; the performance of the BvN switch becomes less predictable when the input traffic is bursty. In this paper, we propose a deflection-compensated BvN (D-BvN) switch architecture to enhance the quasi-static scheduling based on BvN decomposition. The D-BvN switches provide capacity guarantee for virtual circuits (VCs) and deflect bursty traffic when overflow occurs. The deflection scheme is devised to offset the excessive buffer requirement of each VC when input traffic is…
We consider data losses in a single node of a packet-switched Internet-like network. We employ two distinct models, one with discrete and the other with continuous one-dimensional random walks, representing the state of a queue in a router. Both models {have} a built-in critical behavior with {a sharp} transition from exponentially small to finite losses. It turns out that the finite capacity of a buffer and the packet-dropping procedure give rise to specific boundary conditions which lead to strong loss rate fluctuations at the critical point even in the absence of such fluctuations in the da…
