发表机构
University of California, Santa Cruz（加州大学圣克鲁兹分校）
机构由 AI 辅助整理，请以论文原文为准。AI 中文总结
本文提出piSlip调度器，改进iSlip以处理分组与信元混合数据，通过修改授权指针和虚拟直通降低输出延迟，仿真验证其延迟优于iSlip且缓冲需求相近。
AI 中文摘要
本文研究了在分组与信元混合数据下的输入/输出缓冲交叉开关交换机。我们的交换机架构采用输入缓冲和虚拟输出队列以避免头阻塞。交换结构是无加速的交叉开关。我们使用一种针对分组数据改进的iSlip [McKeown]交叉开关调度器，称为piSlip。信元端口在很大程度上保持标准iSlip行为不变。对于分组输出端口，我们引入了对授权指针的修改，以最小化由分组重组引起的输出延迟。我们的模型使用多种输出状态，包括分组直通。仿真结果表明，具有虚拟直通的piSlip在延迟特性上显著优于具有类似分组端口接口的未修改iSlip。仿真还表明，piSlip和iSlip在最大和平均缓冲需求上相似。
英文摘要
This paper examines input/output buffered crossbar switches under combined packet and cell data. Our switch architecture uses input buffering with Virtual Output Queues to avoid Head of Line Blocking. The switch fabric is a crossbar with no speedup. We use a modified iSlip [McKeown] crossbar scheduler geared towards packet data, called piSlip. Cell ports are largely unmodified from standard iSlip behavior. For packet output ports, we introduce changes to the grant pointer which minimizes output latency caused by packet reassembly. Our model uses several output states, including packet cut-through. From simulation results, we show that piSlip with virtual cut-through offers latency characteristics significantly better than unmodified iSlip with similar packet port interfaces. Simulation further shows that piSlip and iSlip have similar maximum and average buffering requirements.
