TREA：低精度时间复用、资源高效的边缘加速器用于目标检测与分类
TREA: Low-precision Time-Multiplexed, Resource-Efficient Edge Accelerator for Object Detection and Classification
AI总结：
TREA通过低精度时间复用和资源高效架构，提升边缘视觉平台在面积、功耗和延迟上的性能，采用双精度SIMD乘累加单元和结构化硬件感知剪枝策略，实现显著的延迟降低和能效提升。
摘要：
本文提出TREA，一种低精度时间复用、资源高效的边缘AI加速器，用于目标检测与分类，旨在满足边缘视觉平台对面积、功耗和延迟的严格约束。所提出的架构集成了基于最高有效位优先（MSDF）移位加法计算的双精度（4/8位）SIMD乘累加（DQ-MAC）单元，结合运行时位截断，消除了传统乘法器开销并减少了累加器位宽。DQ-MAC支持每周期4次FxP4或1次FxP8操作，实现高达4倍的吞吐量提升，无需硬件复制。结构化硬件感知减枝（SHARP）策略与SIMD数据路径协同设计，实现接近50%的结构稀疏性，同时保持完整的MAC利用率。这使得3x3卷积核在FxP4模式下可在1周期内完成，而FxP8模式下需9周期；5x5卷积核在FxP4模式下需3周期，而FxP8模式下需25周期，从而在核级别实现高达9倍的延迟降低。加速器进一步集成了可重构的CORDIC基非线性激活函数（RQ-NAF）核心，具有9级流水线，支持Sigmoid、Tanh和ReLU在每输出周期后通过流水线填充启用，同时通过时间复用实现（N-1）次硬件复用。完整的TREA架构采用1D阵列的100个SIMD DQ-MAC单元，通过层间硬件复用显著减少了面积和控制复杂性。实验结果表明，与传统固定精度和非可重构加速器相比，TREA在延迟、硬件利用率和能效方面均有显著提升，验证了其作为实时边缘视觉工作负载有效解决方案的有效性。
英文摘要：
This work presents TREA, a low-precision time-multiplexed and resource-efficient edge-AI accelerator for object detection and classification, targeting stringent area-power-latency constraints of edge vision platforms. The proposed architecture integrates a dual-precision (4/8-bit) SIMD multiply-accumulate (DQ-MAC) unit based on most-significant-digit-first (MSDF) shift-and-add computation with run-time bit truncation, eliminating conventional multiplier overhead and reducing accumulator bit-width. The DQ-MAC supports 4x FxP4 or 1x FxP8 operations per cycle, achieving up to 4x throughput improvement without hardware duplication. A structured hardware-aware reductive pruning (SHARP) strategy is co-designed with the SIMD datapath, enabling near 50% structured sparsity while maintaining full MAC utilization. This allows a 3x3 convolution kernel to be computed in 1 cycle in FxP4 mode compared to 9 cycles in FxP8, and a 5x5 kernel in 3 cycles versus 25 cycles, yielding up to 9x latency reduction at the kernel level. The accelerator further incorporates a reconfigurable CORDIC-based nonlinear activation function (RQ-NAF) core with a 9-stage pipeline, supporting Sigmoid, Tanh, and ReLU at one output per cycle after pipeline fill, while enabling (N-1) hardware reuse through time-multiplexing. The complete TREA architecture employs a 1D array of 100 SIMD DQ-MAC units with layer-wise hardware reuse, significantly reducing area and control complexity. Experimental results demonstrate substantial improvements in latency, hardware utilization, and energy efficiency compared to conventional fixed-precision and non-reconfigurable accelerators, validating TREA as an effective solution for real-time edge vision workloads.
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